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drm/amd/display: Add register definitions for Beige Goby 

[Why&How]
Adds registers definitions required for Beige Goby initial support.

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Chris Park <Chris.Park@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Aurabindo Pillai 2021-03-15 14:56:11 -04:00 committed by Alex Deucher
parent 2db8378f09
commit 8198ace7a0
4 changed files with 45172 additions and 0 deletions
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8446
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h Normal file
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35344
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_sh_mask.h Normal file
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197
drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_3_0_3_offset.h Normal file
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#ifndef _dpcs_3_0_3_OFFSET_HEADER
#define _dpcs_3_0_3_OFFSET_HEADER
// addressBlock: dpcssys_dpcs0_dpcstx0_dispdec
// base address: 0x0
#define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL 0x2928
#define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_TX_CNTL 0x2929
#define mmDPCSTX0_DPCSTX_TX_CNTL_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_CBUS_CNTL 0x292a
#define mmDPCSTX0_DPCSTX_CBUS_CNTL_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL 0x292b
#define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR 0x292c
#define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA 0x292d
#define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_rdpcstx0_dispdec
// base address: 0x0
#define mmRDPCSTX0_RDPCSTX_CNTL 0x2930
#define mmRDPCSTX0_RDPCSTX_CNTL_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL 0x2931
#define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL 0x2932
#define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA 0x2933
#define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmRDPCSTX0_RDPCS_TX_CR_ADDR 0x2934
#define mmRDPCSTX0_RDPCS_TX_CR_ADDR_BASE_IDX 2
#define mmRDPCSTX0_RDPCS_TX_CR_DATA 0x2935
#define mmRDPCSTX0_RDPCS_TX_CR_DATA_BASE_IDX 2
#define mmRDPCSTX0_RDPCS_TX_SRAM_CNTL 0x2936
#define mmRDPCSTX0_RDPCS_TX_SRAM_CNTL_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_SCRATCH 0x2937
#define mmRDPCSTX0_RDPCSTX_SCRATCH_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_SPARE 0x2938
#define mmRDPCSTX0_RDPCSTX_SPARE_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_CNTL2 0x2939
#define mmRDPCSTX0_RDPCSTX_CNTL2_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x293c
#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL0 0x2940
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL0_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL1 0x2941
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL1_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL2 0x2942
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL2_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL3 0x2943
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL4 0x2944
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL4_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL5 0x2945
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL5_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL6 0x2946
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL7 0x2947
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL7_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL8 0x2948
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL8_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL9 0x2949
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL9_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL10 0x294a
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL10_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL11 0x294b
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL11_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL12 0x294c
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL12_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL13 0x294d
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL13_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL14 0x294e
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL14_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE0 0x294f
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE0_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE1 0x2950
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE1_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE2 0x2951
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE2_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE3 0x2952
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE3_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL 0x2953
#define mmRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2954
#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2955
#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG 0x2956
#define mmRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2
// addressBlock: dpcssys_dpcssys_cr0_dispdec
// base address: 0x0
#define mmDPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
#define mmDPCSSYS_CR0_DPCSSYS_CR_ADDR_BASE_IDX 2
#define mmDPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
#define mmDPCSSYS_CR0_DPCSSYS_CR_DATA_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_dpcstx1_dispdec
// base address: 0x360
#define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL 0x2a00
#define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2
#define mmDPCSTX1_DPCSTX_TX_CNTL 0x2a01
#define mmDPCSTX1_DPCSTX_TX_CNTL_BASE_IDX 2
#define mmDPCSTX1_DPCSTX_CBUS_CNTL 0x2a02
#define mmDPCSTX1_DPCSTX_CBUS_CNTL_BASE_IDX 2
#define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL 0x2a03
#define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2
#define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR 0x2a04
#define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2
#define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA 0x2a05
#define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_rdpcstx1_dispdec
// base address: 0x360
#define mmRDPCSTX1_RDPCSTX_CNTL 0x2a08
#define mmRDPCSTX1_RDPCSTX_CNTL_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL 0x2a09
#define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL 0x2a0a
#define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA 0x2a0b
#define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmRDPCSTX1_RDPCS_TX_CR_ADDR 0x2a0c
#define mmRDPCSTX1_RDPCS_TX_CR_ADDR_BASE_IDX 2
#define mmRDPCSTX1_RDPCS_TX_CR_DATA 0x2a0d
#define mmRDPCSTX1_RDPCS_TX_CR_DATA_BASE_IDX 2
#define mmRDPCSTX1_RDPCS_TX_SRAM_CNTL 0x2a0e
#define mmRDPCSTX1_RDPCS_TX_SRAM_CNTL_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_SCRATCH 0x2a0f
#define mmRDPCSTX1_RDPCSTX_SCRATCH_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_SPARE 0x2a10
#define mmRDPCSTX1_RDPCSTX_SPARE_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_CNTL2 0x2a11
#define mmRDPCSTX1_RDPCSTX_CNTL2_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2a14
#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL0 0x2a18
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL0_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL1 0x2a19
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL1_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL2 0x2a1a
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL2_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL3 0x2a1b
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL4 0x2a1c
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL4_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL5 0x2a1d
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL5_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL6 0x2a1e
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL7 0x2a1f
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL7_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL8 0x2a20
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL8_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL9 0x2a21
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL9_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL10 0x2a22
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL10_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL11 0x2a23
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL11_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL12 0x2a24
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL12_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL13 0x2a25
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL13_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL14 0x2a26
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL14_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE0 0x2a27
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE0_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE1 0x2a28
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE1_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE2 0x2a29
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE2_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE3 0x2a2a
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE3_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL 0x2a2b
#define mmRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2a2c
#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2a2d
#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG 0x2a2e
#define mmRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2
// addressBlock: dpcssys_dpcssys_cr1_dispdec
// base address: 0x360
#define mmDPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
#define mmDPCSSYS_CR1_DPCSSYS_CR_ADDR_BASE_IDX 2
#define mmDPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
#define mmDPCSSYS_CR1_DPCSSYS_CR_DATA_BASE_IDX 2
#endif

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drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_3_0_3_sh_mask.h Normal file
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