mmc: tmio-mmc: add support for 32bit data port
For the r7s72100 SOC, the DATA_PORT register was changed to 32-bits wide. Therefore a new flag has been created that will allow 32-bit reads/writes to the DATA_PORT register instead of 16-bit (because 16-bits accesses are not supported). Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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@ -245,6 +245,12 @@ static inline u32 sd_ctrl_read16_and_16_as_32(struct tmio_mmc_host *host, int ad
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readw(host->ctl + ((addr + 2) << host->bus_shift)) << 16;
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readw(host->ctl + ((addr + 2) << host->bus_shift)) << 16;
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}
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}
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static inline void sd_ctrl_read32_rep(struct tmio_mmc_host *host, int addr,
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u32 *buf, int count)
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{
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readsl(host->ctl + (addr << host->bus_shift), buf, count);
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}
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static inline void sd_ctrl_write16(struct tmio_mmc_host *host, int addr, u16 val)
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static inline void sd_ctrl_write16(struct tmio_mmc_host *host, int addr, u16 val)
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{
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{
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/* If there is a hook and it returns non-zero then there
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/* If there is a hook and it returns non-zero then there
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@ -267,4 +273,10 @@ static inline void sd_ctrl_write32_as_16_and_16(struct tmio_mmc_host *host, int
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writew(val >> 16, host->ctl + ((addr + 2) << host->bus_shift));
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writew(val >> 16, host->ctl + ((addr + 2) << host->bus_shift));
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}
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}
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static inline void sd_ctrl_write32_rep(struct tmio_mmc_host *host, int addr,
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const u32 *buf, int count)
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{
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writesl(host->ctl + (addr << host->bus_shift), buf, count);
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}
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#endif
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#endif
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@ -393,6 +393,36 @@ static void tmio_mmc_transfer_data(struct tmio_mmc_host *host,
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/*
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/*
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* Transfer the data
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* Transfer the data
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*/
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*/
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if (host->pdata->flags & TMIO_MMC_32BIT_DATA_PORT) {
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u8 data[4] = { };
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if (is_read)
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sd_ctrl_read32_rep(host, CTL_SD_DATA_PORT, (u32 *)buf,
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count >> 2);
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else
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sd_ctrl_write32_rep(host, CTL_SD_DATA_PORT, (u32 *)buf,
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count >> 2);
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/* if count was multiple of 4 */
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if (!(count & 0x3))
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return;
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buf8 = (u8 *)(buf + (count >> 2));
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count %= 4;
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if (is_read) {
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sd_ctrl_read32_rep(host, CTL_SD_DATA_PORT,
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(u32 *)data, 1);
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memcpy(buf8, data, count);
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} else {
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memcpy(data, buf8, count);
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sd_ctrl_write32_rep(host, CTL_SD_DATA_PORT,
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(u32 *)data, 1);
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}
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return;
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}
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if (is_read)
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if (is_read)
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sd_ctrl_read16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
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sd_ctrl_read16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
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else
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else
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@ -99,6 +99,11 @@
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*/
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*/
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#define TMIO_MMC_SDIO_STATUS_QUIRK (1 << 8)
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#define TMIO_MMC_SDIO_STATUS_QUIRK (1 << 8)
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/*
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* Some controllers have a 32-bit wide data port register
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*/
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#define TMIO_MMC_32BIT_DATA_PORT (1 << 9)
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/*
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/*
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* Some controllers allows to set SDx actual clock
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* Some controllers allows to set SDx actual clock
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*/
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*/
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