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drm/i915: Remove the definitions for Primary Ring Buffer 

We only ever used the PRB0, neglecting the secondary ring buffers, and
now with the advent of multiple engines with separate ring buffers we
need to excise the anachronisms from our code (and be explicit about
which ring we mean where). This is doubly important in light of the
FORCEWAKE required to read ring buffer registers on SandyBridge.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Chris Wilson 2010-11-11 17:54:52 +00:00
parent e74cfed521
commit 8168bd48bb
4 changed files with 27 additions and 25 deletions
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4
drivers/gpu/drm/i915/i915_dma.c
View File

@ -106,8 +106,8 @@ void i915_kernel_lost_context(struct drm_device * dev)
if (drm_core_check_feature(dev, DRIVER_MODESET))
return;
ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
ring->space = ring->head - (ring->tail + 8);
if (ring->space < 0)
ring->space += ring->size;

28
drivers/gpu/drm/i915/i915_irq.c
View File

@ -520,30 +520,30 @@ i915_get_bbaddr(struct drm_device *dev, u32 *ring)
}
static u32
i915_ringbuffer_last_batch(struct drm_device *dev)
i915_ringbuffer_last_batch(struct drm_device *dev,
struct intel_ring_buffer *ring)
{
struct drm_i915_private *dev_priv = dev->dev_private;
u32 head, bbaddr;
u32 *ring;
u32 *val;
/* Locate the current position in the ringbuffer and walk back
* to find the most recently dispatched batch buffer.
*/
bbaddr = 0;
head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
ring = (u32 *)(dev_priv->render_ring.virtual_start + head);
head = I915_READ_HEAD(ring) & HEAD_ADDR;
val = (u32 *)(ring->virtual_start + head);
while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
bbaddr = i915_get_bbaddr(dev, ring);
while (--val >= (u32 *)ring->virtual_start) {
bbaddr = i915_get_bbaddr(dev, val);
if (bbaddr)
break;
}
if (bbaddr == 0) {
ring = (u32 *)(dev_priv->render_ring.virtual_start
+ dev_priv->render_ring.size);
while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
bbaddr = i915_get_bbaddr(dev, ring);
val = (u32 *)(ring->virtual_start + ring->size);
while (--val >= (u32 *)ring->virtual_start) {
bbaddr = i915_get_bbaddr(dev, val);
if (bbaddr)
break;
}
@ -628,7 +628,7 @@ static void i915_capture_error_state(struct drm_device *dev)
error->bbaddr = 0;
}
bbaddr = i915_ringbuffer_last_batch(dev);
bbaddr = i915_ringbuffer_last_batch(dev, &dev_priv->render_ring);
/* Grab the current batchbuffer, most likely to have crashed. */
batchbuffer[0] = NULL;
@ -1398,10 +1398,10 @@ void i915_hangcheck_elapsed(unsigned long data)
* and break the hang. This should work on
* all but the second generation chipsets.
*/
u32 tmp = I915_READ(PRB0_CTL);
struct intel_ring_buffer *ring = &dev_priv->render_ring;
u32 tmp = I915_READ_CTL(ring);
if (tmp & RING_WAIT) {
I915_WRITE(PRB0_CTL, tmp);
POSTING_READ(PRB0_CTL);
I915_WRITE_CTL(ring, tmp);
goto repeat;
}
}

10
drivers/gpu/drm/i915/i915_reg.h
View File

@ -256,10 +256,6 @@
* Instruction and interrupt control regs
*/
#define PGTBL_ER 0x02024
#define PRB0_TAIL 0x02030
#define PRB0_HEAD 0x02034
#define PRB0_START 0x02038
#define PRB0_CTL 0x0203c
#define RENDER_RING_BASE 0x02000
#define BSD_RING_BASE 0x04000
#define GEN6_BSD_RING_BASE 0x12000
@ -285,10 +281,16 @@
#define RING_INVALID 0x00000000
#define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */
#define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */
#if 0
#define PRB0_TAIL 0x02030
#define PRB0_HEAD 0x02034
#define PRB0_START 0x02038
#define PRB0_CTL 0x0203c
#define PRB1_TAIL 0x02040 /* 915+ only */
#define PRB1_HEAD 0x02044 /* 915+ only */
#define PRB1_START 0x02048 /* 915+ only */
#define PRB1_CTL 0x0204c /* 915+ only */
#endif
#define IPEIR_I965 0x02064
#define IPEHR_I965 0x02068
#define INSTDONE_I965 0x0206c

10
drivers/gpu/drm/i915/intel_display.c
View File

@ -1983,17 +1983,17 @@ static void intel_flush_display_plane(struct drm_device *dev,
static void intel_clear_scanline_wait(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_ring_buffer *ring;
u32 tmp;
if (IS_GEN2(dev))
/* Can't break the hang on i8xx */
return;
tmp = I915_READ(PRB0_CTL);
if (tmp & RING_WAIT) {
I915_WRITE(PRB0_CTL, tmp);
POSTING_READ(PRB0_CTL);
}
ring = &dev_priv->render_ring;
tmp = I915_READ_CTL(ring);
if (tmp & RING_WAIT)
I915_WRITE_CTL(ring, tmp);
}
static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)