drm/amd/powerplay: implement smu_init[fini]_smc_tables for smu11
Each SMU IP may have a different number of SMU tables, so these tables are allocated using dynamic memory Signed-off-by: Kevin Wang <Kevin1.Wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -115,6 +115,19 @@ static int smu_smc_table_sw_init(struct smu_context *smu)
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return 0;
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}
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static int smu_smc_table_sw_fini(struct smu_context *smu)
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{
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int ret;
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ret = smu_fini_smc_tables(smu);
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if (ret) {
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pr_err("Failed to smu_fini_smc_tables!\n");
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return ret;
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}
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return 0;
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}
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static int smu_sw_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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@ -142,10 +155,18 @@ static int smu_sw_init(void *handle)
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static int smu_sw_fini(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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struct smu_context *smu = &adev->smu;
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int ret;
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if (adev->asic_type < CHIP_VEGA20)
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return -EINVAL;
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ret = smu_smc_table_sw_fini(smu);
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if (ret) {
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pr_err("Failed to sw fini smc table!\n");
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return ret;
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}
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return 0;
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}
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@ -24,10 +24,29 @@
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#include "amdgpu.h"
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#define SMU_TABLE_INIT(tables, table_id, s, a, d) \
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do { \
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tables[table_id].size = s; \
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tables[table_id].align = a; \
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tables[table_id].domain = d; \
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} while (0)
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struct smu_table {
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uint64_t size;
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uint32_t align;
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uint8_t domain;
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uint64_t mc_address;
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void *cpu_addr;
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struct amdgpu_bo *bo;
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};
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struct smu_table_context
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{
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void *power_play_table;
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uint32_t power_play_table_size;
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struct smu_table *tables;
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uint32_t table_count;
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};
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struct smu_context
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@ -44,6 +63,7 @@ struct smu_funcs
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{
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int (*init_microcode)(struct smu_context *smu);
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int (*init_smc_tables)(struct smu_context *smu);
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int (*fini_smc_tables)(struct smu_context *smu);
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int (*init_power)(struct smu_context *smu);
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int (*load_microcode)(struct smu_context *smu);
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int (*check_fw_status)(struct smu_context *smu);
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@ -69,6 +89,8 @@ struct smu_funcs
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((smu)->funcs->init_microcode ? (smu)->funcs->init_microcode((smu)) : 0)
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#define smu_init_smc_tables(smu) \
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((smu)->funcs->init_smc_tables ? (smu)->funcs->init_smc_tables((smu)) : 0)
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#define smu_fini_smc_tables(smu) \
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((smu)->funcs->fini_smc_tables ? (smu)->funcs->fini_smc_tables((smu)) : 0)
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#define smu_init_power(smu) \
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((smu)->funcs->init_power ? (smu)->funcs->init_power((smu)) : 0)
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#define smu_load_microcode(smu) \
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@ -234,6 +234,47 @@ static int smu_v11_0_read_pptable_from_vbios(struct smu_context *smu)
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return 0;
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}
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static int smu_v11_0_init_smc_tables(struct smu_context *smu)
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{
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struct smu_table_context *smu_table = &smu->smu_table;
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struct smu_table *tables = NULL;
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if (smu_table->tables || smu_table->table_count != 0)
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return -EINVAL;
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tables = kcalloc(TABLE_COUNT, sizeof(struct smu_table), GFP_KERNEL);
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if (!tables)
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return -ENOMEM;
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smu_table->tables = tables;
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smu_table->table_count = TABLE_COUNT;
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SMU_TABLE_INIT(tables, TABLE_PPTABLE, sizeof(PPTable_t),
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PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
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SMU_TABLE_INIT(tables, TABLE_WATERMARKS, sizeof(Watermarks_t),
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PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
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SMU_TABLE_INIT(tables, TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
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PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
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SMU_TABLE_INIT(tables, TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
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PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
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return 0;
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}
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static int smu_v11_0_fini_smc_tables(struct smu_context *smu)
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{
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struct smu_table_context *smu_table = &smu->smu_table;
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if (!smu_table->tables || smu_table->table_count == 0)
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return -EINVAL;
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kfree(smu_table->tables);
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smu_table->tables = NULL;
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smu_table->table_count = 0;
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return 0;
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}
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static const struct smu_funcs smu_v11_0_funcs = {
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.init_microcode = smu_v11_0_init_microcode,
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.load_microcode = smu_v11_0_load_microcode,
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@ -242,6 +283,8 @@ static const struct smu_funcs smu_v11_0_funcs = {
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.send_smc_msg = smu_v11_0_send_msg,
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.send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
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.read_pptable_from_vbios = smu_v11_0_read_pptable_from_vbios,
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.init_smc_tables = smu_v11_0_init_smc_tables,
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.fini_smc_tables = smu_v11_0_fini_smc_tables,
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};
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void smu_v11_0_set_smu_funcs(struct smu_context *smu)
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