mtd: cfi_cmdset_0001.c: add support for Sharp LH28F640BF NOR
This family of chips was long ago supported by the pre-cfi driver.
CFI code tested on several Zaurus SL-5500 (Collie) 2x16 on 32 bit bus.
Function is_LH28F640BF() mimics is_m29ew() from cmdset_0002.c
Buffer write fixes as seen in 2007 patch c/o
Anti Sullin <anti.sullin <at> artecdesign.ee>
http://comments.gmane.org/gmane.linux.ports.arm.kernel/36733
[Brian: this patch is semi-urgent, because the following patch switches
to using CFI detection for a chip which (until now) is unsupported by
the CFI driver
9218310
ARM: 8084/1: sa1100: collie: revert back to cfi_probe
]
Signed-off-by: Andrea Adami <andrea.adami@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This commit is contained in:
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@ -52,6 +52,11 @@
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/* Atmel chips */
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#define AT49BV640D 0x02de
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#define AT49BV640DT 0x02db
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/* Sharp chips */
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#define LH28F640BFHE_PTTL90 0x00b0
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#define LH28F640BFHE_PBTL90 0x00b1
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#define LH28F640BFHE_PTTL70A 0x00b2
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#define LH28F640BFHE_PBTL70A 0x00b3
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static int cfi_intelext_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
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static int cfi_intelext_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
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@ -258,6 +263,36 @@ static void fixup_st_m28w320cb(struct mtd_info *mtd)
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(cfi->cfiq->EraseRegionInfo[1] & 0xffff0000) | 0x3e;
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};
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static int is_LH28F640BF(struct cfi_private *cfi)
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{
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/* Sharp LH28F640BF Family */
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if (cfi->mfr == CFI_MFR_SHARP && (
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cfi->id == LH28F640BFHE_PTTL90 || cfi->id == LH28F640BFHE_PBTL90 ||
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cfi->id == LH28F640BFHE_PTTL70A || cfi->id == LH28F640BFHE_PBTL70A))
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return 1;
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return 0;
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}
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static void fixup_LH28F640BF(struct mtd_info *mtd)
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{
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struct map_info *map = mtd->priv;
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struct cfi_private *cfi = map->fldrv_priv;
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struct cfi_pri_intelext *extp = cfi->cmdset_priv;
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/* Reset the Partition Configuration Register on LH28F640BF
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* to a single partition (PCR = 0x000): PCR is embedded into A0-A15. */
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if (is_LH28F640BF(cfi)) {
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printk(KERN_INFO "Reset Partition Config. Register: 1 Partition of 4 planes\n");
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map_write(map, CMD(0x60), 0);
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map_write(map, CMD(0x04), 0);
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/* We have set one single partition thus
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* Simultaneous Operations are not allowed */
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printk(KERN_INFO "cfi_cmdset_0001: Simultaneous Operations disabled\n");
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extp->FeatureSupport &= ~512;
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}
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}
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static void fixup_use_point(struct mtd_info *mtd)
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{
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struct map_info *map = mtd->priv;
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@ -309,6 +344,8 @@ static struct cfi_fixup cfi_fixup_table[] = {
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{ CFI_MFR_ST, 0x00ba, /* M28W320CT */ fixup_st_m28w320ct },
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{ CFI_MFR_ST, 0x00bb, /* M28W320CB */ fixup_st_m28w320cb },
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{ CFI_MFR_INTEL, CFI_ID_ANY, fixup_unlock_powerup_lock },
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{ CFI_MFR_SHARP, CFI_ID_ANY, fixup_unlock_powerup_lock },
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{ CFI_MFR_SHARP, CFI_ID_ANY, fixup_LH28F640BF },
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{ 0, 0, NULL }
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};
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@ -1649,6 +1686,12 @@ static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
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initial_adr = adr;
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cmd_adr = adr & ~(wbufsize-1);
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/* Sharp LH28F640BF chips need the first address for the
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* Page Buffer Program command. See Table 5 of
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* LH28F320BF, LH28F640BF, LH28F128BF Series (Appendix FUM00701) */
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if (is_LH28F640BF(cfi))
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cmd_adr = adr;
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/* Let's determine this according to the interleave only once */
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write_cmd = (cfi->cfiq->P_ID != P_ID_INTEL_PERFORMANCE) ? CMD(0xe8) : CMD(0xe9);
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