drm/amd/amdgpu: add RLC firmware to support raven1 refresh
Use SMU firmware version to indentify the raven1 refresh device and then load homologous RLC FW. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Suggested-by: Huang Rui<Ray.Huang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1631,6 +1631,7 @@ static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
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{
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{
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int r = 0;
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int r = 0;
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int i;
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int i;
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uint32_t smu_version;
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if (adev->asic_type >= CHIP_VEGA10) {
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if (adev->asic_type >= CHIP_VEGA10) {
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for (i = 0; i < adev->num_ip_blocks; i++) {
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for (i = 0; i < adev->num_ip_blocks; i++) {
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@ -1656,16 +1657,9 @@ static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
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}
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}
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}
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}
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}
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}
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r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
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if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->load_firmware) {
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return r;
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r = adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle);
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if (r) {
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pr_err("firmware loading failed\n");
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return r;
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}
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}
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return 0;
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}
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}
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/**
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/**
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@ -2698,6 +2698,21 @@ void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
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}
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}
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int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version)
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{
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int r = -EINVAL;
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if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->load_firmware) {
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r = adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle);
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if (r) {
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pr_err("smu firmware loading failed\n");
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return r;
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}
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*smu_version = adev->pm.fw_version;
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}
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return r;
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}
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int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
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int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
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{
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{
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struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
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struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
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@ -34,6 +34,7 @@ void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev);
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int amdgpu_pm_sysfs_init(struct amdgpu_device *adev);
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int amdgpu_pm_sysfs_init(struct amdgpu_device *adev);
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void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev);
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void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev);
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void amdgpu_pm_print_power_states(struct amdgpu_device *adev);
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void amdgpu_pm_print_power_states(struct amdgpu_device *adev);
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int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version);
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void amdgpu_pm_compute_clocks(struct amdgpu_device *adev);
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void amdgpu_pm_compute_clocks(struct amdgpu_device *adev);
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void amdgpu_dpm_thermal_work_handler(struct work_struct *work);
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void amdgpu_dpm_thermal_work_handler(struct work_struct *work);
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void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable);
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void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable);
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@ -28,6 +28,7 @@
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#include "soc15.h"
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#include "soc15.h"
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#include "soc15d.h"
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#include "soc15d.h"
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#include "amdgpu_atomfirmware.h"
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#include "amdgpu_atomfirmware.h"
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#include "amdgpu_pm.h"
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#include "gc/gc_9_0_offset.h"
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#include "gc/gc_9_0_offset.h"
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#include "gc/gc_9_0_sh_mask.h"
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#include "gc/gc_9_0_sh_mask.h"
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@ -97,6 +98,7 @@ MODULE_FIRMWARE("amdgpu/raven2_me.bin");
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MODULE_FIRMWARE("amdgpu/raven2_mec.bin");
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MODULE_FIRMWARE("amdgpu/raven2_mec.bin");
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MODULE_FIRMWARE("amdgpu/raven2_mec2.bin");
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MODULE_FIRMWARE("amdgpu/raven2_mec2.bin");
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MODULE_FIRMWARE("amdgpu/raven2_rlc.bin");
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MODULE_FIRMWARE("amdgpu/raven2_rlc.bin");
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MODULE_FIRMWARE("amdgpu/raven_kicker_rlc.bin");
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static const struct soc15_reg_golden golden_settings_gc_9_0[] =
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static const struct soc15_reg_golden golden_settings_gc_9_0[] =
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{
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{
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@ -591,7 +593,8 @@ static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev)
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case CHIP_RAVEN:
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case CHIP_RAVEN:
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if (adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)
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if (adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)
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break;
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break;
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if ((adev->gfx.rlc_fw_version < 531) ||
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if ((adev->gfx.rlc_fw_version != 106 &&
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adev->gfx.rlc_fw_version < 531) ||
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(adev->gfx.rlc_fw_version == 53815) ||
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(adev->gfx.rlc_fw_version == 53815) ||
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(adev->gfx.rlc_feature_version < 1) ||
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(adev->gfx.rlc_feature_version < 1) ||
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!adev->gfx.rlc.is_rlc_v2_1)
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!adev->gfx.rlc.is_rlc_v2_1)
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@ -615,6 +618,7 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
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unsigned int i = 0;
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unsigned int i = 0;
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uint16_t version_major;
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uint16_t version_major;
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uint16_t version_minor;
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uint16_t version_minor;
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uint32_t smu_version;
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DRM_DEBUG("\n");
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DRM_DEBUG("\n");
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@ -685,6 +689,12 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
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(((adev->pdev->revision >= 0xC8) && (adev->pdev->revision <= 0xCF)) ||
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(((adev->pdev->revision >= 0xC8) && (adev->pdev->revision <= 0xCF)) ||
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((adev->pdev->revision >= 0xD8) && (adev->pdev->revision <= 0xDF))))
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((adev->pdev->revision >= 0xD8) && (adev->pdev->revision <= 0xDF))))
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snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc_am4.bin", chip_name);
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snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc_am4.bin", chip_name);
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else if (!strcmp(chip_name, "raven") && (amdgpu_pm_load_smu_firmware(adev, &smu_version) == 0) &&
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(smu_version >= 0x41e2b))
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/**
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*SMC is loaded by SBIOS on APU and it's able to get the SMU version directly.
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*/
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snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_kicker_rlc.bin", chip_name);
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else
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else
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snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
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snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
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err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
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err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
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