ncr5380: Merge DMA implementation from atari_NCR5380 core driver
Adopt the DMA implementation from atari_NCR5380.c. This means that atari_scsi and sun3_scsi can make use of the NCR5380.c core driver and the atari_NCR5380.c driver fork can be made redundant. Signed-off-by: Finn Thain <fthain@telegraphics.com.au> Reviewed-by: Hannes Reinecke <hare@suse.com> Tested-by: Michael Schmitz <schmitzmic@gmail.com> Tested-by: Ondrej Zary <linux@rainbow-software.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
parent
438af51c64
commit
8053b0ee79
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@ -31,9 +31,6 @@
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/*
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/*
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* Further development / testing that should be done :
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* Further development / testing that should be done :
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* 1. Cleanup the NCR5380_transfer_dma function and DMA operation complete
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* code so that everything does the same thing that's done at the
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* end of a pseudo-DMA read operation.
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*
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*
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* 4. Test SCSI-II tagged queueing (I have no devices which support
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* 4. Test SCSI-II tagged queueing (I have no devices which support
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* tagged queueing)
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* tagged queueing)
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@ -117,6 +114,8 @@
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*
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*
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* PSEUDO_DMA - if defined, PSEUDO DMA is used during the data transfer phases.
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* PSEUDO_DMA - if defined, PSEUDO DMA is used during the data transfer phases.
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*
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*
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* REAL_DMA - if defined, REAL DMA is used during the data transfer phases.
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*
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* These macros MUST be defined :
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* These macros MUST be defined :
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*
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*
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* NCR5380_read(register) - read from the specified register
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* NCR5380_read(register) - read from the specified register
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@ -801,6 +800,72 @@ static void NCR5380_main(struct work_struct *work)
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} while (!done);
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} while (!done);
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}
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}
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/*
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* NCR5380_dma_complete - finish DMA transfer
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* @instance: the scsi host instance
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*
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* Called by the interrupt handler when DMA finishes or a phase
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* mismatch occurs (which would end the DMA transfer).
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*/
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static void NCR5380_dma_complete(struct Scsi_Host *instance)
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{
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struct NCR5380_hostdata *hostdata = shost_priv(instance);
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int transferred;
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unsigned char **data;
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int *count;
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int saved_data = 0, overrun = 0;
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unsigned char p;
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if (hostdata->read_overruns) {
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p = hostdata->connected->SCp.phase;
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if (p & SR_IO) {
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udelay(10);
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if ((NCR5380_read(BUS_AND_STATUS_REG) &
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(BASR_PHASE_MATCH | BASR_ACK)) ==
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(BASR_PHASE_MATCH | BASR_ACK)) {
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saved_data = NCR5380_read(INPUT_DATA_REG);
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overrun = 1;
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dsprintk(NDEBUG_DMA, instance, "read overrun handled\n");
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}
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}
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}
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NCR5380_write(MODE_REG, MR_BASE);
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NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
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NCR5380_read(RESET_PARITY_INTERRUPT_REG);
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transferred = hostdata->dma_len - NCR5380_dma_residual(instance);
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hostdata->dma_len = 0;
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data = (unsigned char **)&hostdata->connected->SCp.ptr;
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count = &hostdata->connected->SCp.this_residual;
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*data += transferred;
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*count -= transferred;
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if (hostdata->read_overruns) {
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int cnt, toPIO;
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if ((NCR5380_read(STATUS_REG) & PHASE_MASK) == p && (p & SR_IO)) {
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cnt = toPIO = hostdata->read_overruns;
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if (overrun) {
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dsprintk(NDEBUG_DMA, instance,
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"Got an input overrun, using saved byte\n");
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*(*data)++ = saved_data;
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(*count)--;
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cnt--;
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toPIO--;
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}
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if (toPIO > 0) {
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dsprintk(NDEBUG_DMA, instance,
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"Doing %d byte PIO to 0x%p\n", cnt, *data);
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NCR5380_transfer_pio(instance, &p, &cnt, data);
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*count -= toPIO - cnt;
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}
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}
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}
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}
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#ifndef DONT_USE_INTR
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#ifndef DONT_USE_INTR
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/**
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/**
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@ -855,7 +920,22 @@ static irqreturn_t NCR5380_intr(int irq, void *dev_id)
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dsprintk(NDEBUG_INTR, instance, "IRQ %d, BASR 0x%02x, SR 0x%02x, MR 0x%02x\n",
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dsprintk(NDEBUG_INTR, instance, "IRQ %d, BASR 0x%02x, SR 0x%02x, MR 0x%02x\n",
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irq, basr, sr, mr);
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irq, basr, sr, mr);
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if ((NCR5380_read(CURRENT_SCSI_DATA_REG) & hostdata->id_mask) &&
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if ((mr & MR_DMA_MODE) || (mr & MR_MONITOR_BSY)) {
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/* Probably End of DMA, Phase Mismatch or Loss of BSY.
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* We ack IRQ after clearing Mode Register. Workarounds
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* for End of DMA errata need to happen in DMA Mode.
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*/
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dsprintk(NDEBUG_INTR, instance, "interrupt in DMA mode\n");
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if (hostdata->connected) {
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NCR5380_dma_complete(instance);
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queue_work(hostdata->work_q, &hostdata->main_task);
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} else {
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NCR5380_write(MODE_REG, MR_BASE);
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NCR5380_read(RESET_PARITY_INTERRUPT_REG);
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}
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} else if ((NCR5380_read(CURRENT_SCSI_DATA_REG) & hostdata->id_mask) &&
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(sr & (SR_SEL | SR_IO | SR_BSY | SR_RST)) == (SR_SEL | SR_IO)) {
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(sr & (SR_SEL | SR_IO | SR_BSY | SR_RST)) == (SR_SEL | SR_IO)) {
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/* Probably reselected */
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/* Probably reselected */
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NCR5380_write(SELECT_ENABLE_REG, 0);
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NCR5380_write(SELECT_ENABLE_REG, 0);
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@ -1431,28 +1511,38 @@ static int NCR5380_transfer_dma(struct Scsi_Host *instance,
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register unsigned char p = *phase;
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register unsigned char p = *phase;
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register unsigned char *d = *data;
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register unsigned char *d = *data;
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unsigned char tmp;
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unsigned char tmp;
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int result;
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int result = 0;
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if ((tmp = (NCR5380_read(STATUS_REG) & PHASE_MASK)) != p) {
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if ((tmp = (NCR5380_read(STATUS_REG) & PHASE_MASK)) != p) {
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*phase = tmp;
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*phase = tmp;
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return -1;
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return -1;
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}
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}
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hostdata->connected->SCp.phase = p;
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if (p & SR_IO) {
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if (hostdata->read_overruns)
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c -= hostdata->read_overruns;
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else if (hostdata->flags & FLAG_DMA_FIXUP)
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--c;
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}
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dsprintk(NDEBUG_DMA, instance, "initializing DMA %s: length %d, address %p\n",
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(p & SR_IO) ? "receive" : "send", c, d);
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NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(p));
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NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(p));
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NCR5380_write(MODE_REG, MR_BASE | MR_DMA_MODE | MR_MONITOR_BSY |
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MR_ENABLE_EOP_INTR);
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/*
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if (!(hostdata->flags & FLAG_LATE_DMA_SETUP)) {
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* Note : on my sample board, watch-dog timeouts occurred when interrupts
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/* On the Medusa, it is a must to initialize the DMA before
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* were not disabled for the duration of a single DMA transfer, from
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* starting the NCR. This is also the cleaner way for the TT.
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* before the setting of DMA mode to after transfer of the last byte.
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*/
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*/
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if (p & SR_IO)
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result = NCR5380_dma_recv_setup(instance, d, c);
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if (hostdata->flags & FLAG_DMA_FIXUP)
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else
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NCR5380_write(MODE_REG, MR_BASE | MR_DMA_MODE | MR_MONITOR_BSY);
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result = NCR5380_dma_send_setup(instance, d, c);
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else
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}
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NCR5380_write(MODE_REG, MR_BASE | MR_DMA_MODE | MR_MONITOR_BSY |
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MR_ENABLE_EOP_INTR);
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dprintk(NDEBUG_DMA, "scsi%d : mode reg = 0x%X\n", instance->host_no, NCR5380_read(MODE_REG));
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/*
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/*
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* On the PAS16 at least I/O recovery delays are not needed here.
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* On the PAS16 at least I/O recovery delays are not needed here.
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@ -1470,6 +1560,29 @@ static int NCR5380_transfer_dma(struct Scsi_Host *instance,
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NCR5380_io_delay(1);
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NCR5380_io_delay(1);
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}
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}
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if (hostdata->flags & FLAG_LATE_DMA_SETUP) {
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/* On the Falcon, the DMA setup must be done after the last
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* NCR access, else the DMA setup gets trashed!
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*/
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if (p & SR_IO)
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result = NCR5380_dma_recv_setup(instance, d, c);
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else
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result = NCR5380_dma_send_setup(instance, d, c);
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}
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/* On failure, NCR5380_dma_xxxx_setup() returns a negative int. */
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if (result < 0)
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return result;
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/* For real DMA, result is the byte count. DMA interrupt is expected. */
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if (result > 0) {
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hostdata->dma_len = result;
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return 0;
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}
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/* The result is zero iff pseudo DMA send/receive was completed. */
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hostdata->dma_len = c;
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/*
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/*
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* A note regarding the DMA errata workarounds for early NMOS silicon.
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* A note regarding the DMA errata workarounds for early NMOS silicon.
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*
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*
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@ -1504,10 +1617,8 @@ static int NCR5380_transfer_dma(struct Scsi_Host *instance,
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* request.
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* request.
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*/
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*/
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if (p & SR_IO) {
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if (hostdata->flags & FLAG_DMA_FIXUP) {
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result = NCR5380_dma_recv_setup(instance, d,
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if (p & SR_IO) {
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hostdata->flags & FLAG_DMA_FIXUP ? c - 1 : c);
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if (!result && (hostdata->flags & FLAG_DMA_FIXUP)) {
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/*
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/*
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* The workaround was to transfer fewer bytes than we
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* The workaround was to transfer fewer bytes than we
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* intended to with the pseudo-DMA read function, wait for
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* intended to with the pseudo-DMA read function, wait for
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@ -1533,11 +1644,8 @@ static int NCR5380_transfer_dma(struct Scsi_Host *instance,
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result = -1;
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result = -1;
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shost_printk(KERN_ERR, instance, "PDMA read: !REQ timeout\n");
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shost_printk(KERN_ERR, instance, "PDMA read: !REQ timeout\n");
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}
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}
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d[c - 1] = NCR5380_read(INPUT_DATA_REG);
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d[*count - 1] = NCR5380_read(INPUT_DATA_REG);
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}
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} else {
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} else {
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result = NCR5380_dma_send_setup(instance, d, c);
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if (!result && (hostdata->flags & FLAG_DMA_FIXUP)) {
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/*
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/*
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* Wait for the last byte to be sent. If REQ is being asserted for
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* Wait for the last byte to be sent. If REQ is being asserted for
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* the byte we're interested, we'll ACK it and it will go false.
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* the byte we're interested, we'll ACK it and it will go false.
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@ -1550,11 +1658,8 @@ static int NCR5380_transfer_dma(struct Scsi_Host *instance,
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}
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}
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}
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}
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}
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}
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NCR5380_write(MODE_REG, MR_BASE);
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NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
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NCR5380_dma_complete(instance);
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NCR5380_read(RESET_PARITY_INTERRUPT_REG);
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*data = d + c;
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*count = 0;
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return result;
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return result;
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}
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}
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@ -1667,8 +1772,7 @@ static void NCR5380_information_transfer(struct Scsi_Host *instance)
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do_abort(instance);
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do_abort(instance);
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cmd->result = DID_ERROR << 16;
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cmd->result = DID_ERROR << 16;
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/* XXX - need to source or sink data here, as appropriate */
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/* XXX - need to source or sink data here, as appropriate */
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} else
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}
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cmd->SCp.this_residual -= transfersize - len;
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} else {
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} else {
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/* Break up transfer into 3 ms chunks,
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/* Break up transfer into 3 ms chunks,
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* presuming 6 accesses per handshake.
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* presuming 6 accesses per handshake.
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@ -20,6 +20,7 @@
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#define NCR5380_dma_xfer_len(instance, cmd, phase) (cmd->transfersize)
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#define NCR5380_dma_xfer_len(instance, cmd, phase) (cmd->transfersize)
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#define NCR5380_dma_recv_setup cumanascsi_pread
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#define NCR5380_dma_recv_setup cumanascsi_pread
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#define NCR5380_dma_send_setup cumanascsi_pwrite
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#define NCR5380_dma_send_setup cumanascsi_pwrite
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#define NCR5380_dma_residual(instance) (0)
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#define NCR5380_intr cumanascsi_intr
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#define NCR5380_intr cumanascsi_intr
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#define NCR5380_queue_command cumanascsi_queue_command
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#define NCR5380_queue_command cumanascsi_queue_command
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@ -245,7 +246,7 @@ static int cumanascsi1_probe(struct expansion_card *ec,
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host->irq = ec->irq;
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host->irq = ec->irq;
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ret = NCR5380_init(host, FLAG_DMA_FIXUP);
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ret = NCR5380_init(host, FLAG_DMA_FIXUP | FLAG_LATE_DMA_SETUP);
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if (ret)
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if (ret)
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goto out_unmap;
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goto out_unmap;
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@ -26,6 +26,7 @@
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#define NCR5380_dma_xfer_len(instance, cmd, phase) (0)
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#define NCR5380_dma_xfer_len(instance, cmd, phase) (0)
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#define NCR5380_dma_recv_setup oakscsi_pread
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#define NCR5380_dma_recv_setup oakscsi_pread
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#define NCR5380_dma_send_setup oakscsi_pwrite
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#define NCR5380_dma_send_setup oakscsi_pwrite
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#define NCR5380_dma_residual(instance) (0)
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#define NCR5380_queue_command oakscsi_queue_command
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#define NCR5380_queue_command oakscsi_queue_command
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#define NCR5380_info oakscsi_info
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#define NCR5380_info oakscsi_info
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@ -144,7 +145,7 @@ static int oakscsi_probe(struct expansion_card *ec, const struct ecard_id *id)
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host->irq = NO_IRQ;
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host->irq = NO_IRQ;
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host->n_io_port = 255;
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host->n_io_port = 255;
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ret = NCR5380_init(host, FLAG_DMA_FIXUP);
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ret = NCR5380_init(host, FLAG_DMA_FIXUP | FLAG_LATE_DMA_SETUP);
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if (ret)
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if (ret)
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goto out_unmap;
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goto out_unmap;
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@ -42,6 +42,7 @@
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#define NCR5380_dma_xfer_len(instance, cmd, phase) (0)
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#define NCR5380_dma_xfer_len(instance, cmd, phase) (0)
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#define NCR5380_dma_recv_setup(instance, dst, len) (0)
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#define NCR5380_dma_recv_setup(instance, dst, len) (0)
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#define NCR5380_dma_send_setup(instance, src, len) (0)
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#define NCR5380_dma_send_setup(instance, src, len) (0)
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#define NCR5380_dma_residual(instance) (0)
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#define NCR5380_implementation_fields /* none */
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#define NCR5380_implementation_fields /* none */
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@ -228,7 +228,7 @@ found:
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instance->base = addr;
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instance->base = addr;
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((struct NCR5380_hostdata *)(instance)->hostdata)->base = base;
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((struct NCR5380_hostdata *)(instance)->hostdata)->base = base;
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if (NCR5380_init(instance, 0))
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if (NCR5380_init(instance, FLAG_LATE_DMA_SETUP))
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goto out_unregister;
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goto out_unregister;
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NCR5380_maybe_reset_bus(instance);
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NCR5380_maybe_reset_bus(instance);
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@ -23,6 +23,7 @@
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dtc_dma_xfer_len(cmd)
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dtc_dma_xfer_len(cmd)
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#define NCR5380_dma_recv_setup dtc_pread
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#define NCR5380_dma_recv_setup dtc_pread
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#define NCR5380_dma_send_setup dtc_pwrite
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#define NCR5380_dma_send_setup dtc_pwrite
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#define NCR5380_dma_residual(instance) (0)
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#define NCR5380_intr dtc_intr
|
#define NCR5380_intr dtc_intr
|
||||||
#define NCR5380_queue_command dtc_queue_command
|
#define NCR5380_queue_command dtc_queue_command
|
||||||
|
|
|
@ -466,7 +466,7 @@ static int __init generic_NCR5380_detect(struct scsi_host_template *tpnt)
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
if (NCR5380_init(instance, flags))
|
if (NCR5380_init(instance, flags | FLAG_LATE_DMA_SETUP))
|
||||||
goto out_unregister;
|
goto out_unregister;
|
||||||
|
|
||||||
switch (overrides[current_override].board) {
|
switch (overrides[current_override].board) {
|
||||||
|
|
|
@ -64,6 +64,7 @@
|
||||||
generic_NCR5380_dma_xfer_len(instance, cmd)
|
generic_NCR5380_dma_xfer_len(instance, cmd)
|
||||||
#define NCR5380_dma_recv_setup generic_NCR5380_pread
|
#define NCR5380_dma_recv_setup generic_NCR5380_pread
|
||||||
#define NCR5380_dma_send_setup generic_NCR5380_pwrite
|
#define NCR5380_dma_send_setup generic_NCR5380_pwrite
|
||||||
|
#define NCR5380_dma_residual(instance) (0)
|
||||||
|
|
||||||
#define NCR5380_intr generic_NCR5380_intr
|
#define NCR5380_intr generic_NCR5380_intr
|
||||||
#define NCR5380_queue_command generic_NCR5380_queue_command
|
#define NCR5380_queue_command generic_NCR5380_queue_command
|
||||||
|
|
|
@ -37,6 +37,7 @@
|
||||||
macscsi_dma_xfer_len(instance, cmd)
|
macscsi_dma_xfer_len(instance, cmd)
|
||||||
#define NCR5380_dma_recv_setup macscsi_pread
|
#define NCR5380_dma_recv_setup macscsi_pread
|
||||||
#define NCR5380_dma_send_setup macscsi_pwrite
|
#define NCR5380_dma_send_setup macscsi_pwrite
|
||||||
|
#define NCR5380_dma_residual(instance) (0)
|
||||||
|
|
||||||
#define NCR5380_intr macscsi_intr
|
#define NCR5380_intr macscsi_intr
|
||||||
#define NCR5380_queue_command macscsi_queue_command
|
#define NCR5380_queue_command macscsi_queue_command
|
||||||
|
@ -386,7 +387,7 @@ static int __init mac_scsi_probe(struct platform_device *pdev)
|
||||||
#endif
|
#endif
|
||||||
host_flags |= setup_toshiba_delay > 0 ? FLAG_TOSHIBA_DELAY : 0;
|
host_flags |= setup_toshiba_delay > 0 ? FLAG_TOSHIBA_DELAY : 0;
|
||||||
|
|
||||||
error = NCR5380_init(instance, host_flags);
|
error = NCR5380_init(instance, host_flags | FLAG_LATE_DMA_SETUP);
|
||||||
if (error)
|
if (error)
|
||||||
goto fail_init;
|
goto fail_init;
|
||||||
|
|
||||||
|
|
|
@ -375,7 +375,7 @@ static int __init pas16_detect(struct scsi_host_template *tpnt)
|
||||||
|
|
||||||
instance->io_port = io_port;
|
instance->io_port = io_port;
|
||||||
|
|
||||||
if (NCR5380_init(instance, FLAG_DMA_FIXUP))
|
if (NCR5380_init(instance, FLAG_DMA_FIXUP | FLAG_LATE_DMA_SETUP))
|
||||||
goto out_unregister;
|
goto out_unregister;
|
||||||
|
|
||||||
NCR5380_maybe_reset_bus(instance);
|
NCR5380_maybe_reset_bus(instance);
|
||||||
|
|
|
@ -105,6 +105,7 @@
|
||||||
#define NCR5380_dma_xfer_len(instance, cmd, phase) (cmd->transfersize)
|
#define NCR5380_dma_xfer_len(instance, cmd, phase) (cmd->transfersize)
|
||||||
#define NCR5380_dma_recv_setup pas16_pread
|
#define NCR5380_dma_recv_setup pas16_pread
|
||||||
#define NCR5380_dma_send_setup pas16_pwrite
|
#define NCR5380_dma_send_setup pas16_pwrite
|
||||||
|
#define NCR5380_dma_residual(instance) (0)
|
||||||
|
|
||||||
#define NCR5380_intr pas16_intr
|
#define NCR5380_intr pas16_intr
|
||||||
#define NCR5380_queue_command pas16_queue_command
|
#define NCR5380_queue_command pas16_queue_command
|
||||||
|
|
|
@ -208,7 +208,7 @@ found:
|
||||||
instance->base = base;
|
instance->base = base;
|
||||||
((struct NCR5380_hostdata *)instance->hostdata)->base = p;
|
((struct NCR5380_hostdata *)instance->hostdata)->base = p;
|
||||||
|
|
||||||
if (NCR5380_init(instance, FLAG_DMA_FIXUP))
|
if (NCR5380_init(instance, FLAG_DMA_FIXUP | FLAG_LATE_DMA_SETUP))
|
||||||
goto out_unregister;
|
goto out_unregister;
|
||||||
|
|
||||||
NCR5380_maybe_reset_bus(instance);
|
NCR5380_maybe_reset_bus(instance);
|
||||||
|
|
|
@ -79,6 +79,7 @@
|
||||||
#define NCR5380_dma_xfer_len(instance, cmd, phase) (cmd->transfersize)
|
#define NCR5380_dma_xfer_len(instance, cmd, phase) (cmd->transfersize)
|
||||||
#define NCR5380_dma_recv_setup t128_pread
|
#define NCR5380_dma_recv_setup t128_pread
|
||||||
#define NCR5380_dma_send_setup t128_pwrite
|
#define NCR5380_dma_send_setup t128_pwrite
|
||||||
|
#define NCR5380_dma_residual(instance) (0)
|
||||||
|
|
||||||
#define NCR5380_intr t128_intr
|
#define NCR5380_intr t128_intr
|
||||||
#define NCR5380_queue_command t128_queue_command
|
#define NCR5380_queue_command t128_queue_command
|
||||||
|
|
Loading…
Reference in New Issue