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OpenCloudOS-Kernel
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[ARM] Remove MODE_(SVC|IRQ|FIQ|USR) and DEFAULT_FIQ 

DEFAULT_FIQ was entirely unused.  MODE_* are just redefinitions
of *_MODE.  Use *_MODE instead.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King 2006-06-25 12:01:48 +01:00 committed by Russell King
parent 405040a78b
commit 801194e3bc
7 changed files with 7 additions and 14 deletions
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2
arch/arm/kernel/head-nommu.S
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@ -39,7 +39,7 @@
__INIT
.type stext, %function
ENTRY(stext)
msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC @ ensure svc mode
msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE @ ensure svc mode
@ and irqs disabled
mrc p15, 0, r9, c0, c0 @ get processor id
bl __lookup_processor_type @ r5=procinfo r9=cpuid

4
arch/arm/kernel/head.S
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@ -71,7 +71,7 @@
__INIT
.type stext, %function
ENTRY(stext)
msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC @ ensure svc mode
msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE @ ensure svc mode
@ and irqs disabled
mrc p15, 0, r9, c0, c0 @ get processor id
bl __lookup_processor_type @ r5=procinfo r9=cpuid
@ -104,7 +104,7 @@ ENTRY(secondary_startup)
* the processor type - there is no need to check the machine type
* as it has already been validated by the primary processor.
*/
msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC
msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
mrc p15, 0, r9, c0, c0 @ get processor id
bl __lookup_processor_type
movs r10, r5 @ invalid processor?

2
arch/arm/mach-pxa/sleep.S
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@ -189,7 +189,7 @@ ENTRY(pxa_cpu_suspend)
.data
.align 5
ENTRY(pxa_cpu_resume)
mov r0, #PSR_I_BIT | PSR_F_BIT | MODE_SVC @ set SVC, irqs off
mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE @ set SVC, irqs off
msr cpsr_c, r0
ldr r0, sleep_save_sp @ stack phys addr

2
arch/arm/mach-s3c2410/sleep.S
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@ -128,7 +128,7 @@ s3c2410_sleep_save_phys:
*/
ENTRY(s3c2410_cpu_resume)
mov r0, #PSR_I_BIT | PSR_F_BIT | MODE_SVC
mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
msr cpsr_c, r0
@@ load UART to allow us to print the two characters for

2
arch/arm/mach-sa1100/sleep.S
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@ -177,7 +177,7 @@ sa1110_sdram_controller_fix:
.data
.align 5
ENTRY(sa1100_cpu_resume)
mov r0, #PSR_F_BIT | PSR_I_BIT | MODE_SVC
mov r0, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
msr cpsr_c, r0 @ set SVC, irqs off
ldr r0, sleep_save_sp @ stack phys addr

2
arch/arm/nwfpe/entry26.S
View File

@ -26,7 +26,7 @@
It is called from the kernel with code similar to this:
mov fp, #0
teqp pc, #PSR_I_BIT | MODE_SVC
teqp pc, #PSR_I_BIT | SVC_MODE
ldr r4, .LC2
ldr pc, [r4] @ Call FP module USR entry point

7
include/asm-arm/assembler.h
View File

@ -55,13 +55,6 @@
#define PLD(code...)
#endif
#define MODE_USR USR_MODE
#define MODE_FIQ FIQ_MODE
#define MODE_IRQ IRQ_MODE
#define MODE_SVC SVC_MODE
#define DEFAULT_FIQ MODE_FIQ
/*
* Enable and disable interrupts
*/