irqchip updates for 4.16
- Fix a GICv3 issue when parsing ACPI entries for disabled CPUs - Driver for the MIPS Goldfish virtual platform - Small fixlet for the ompic driver - Interrupt polatiry support for the Raspberry Pi irqchip -----BEGIN PGP SIGNATURE----- iQJJBAABCAAzFiEEn9UcU+C1Yxj9lZw9I9DQutE9ekMFAlpWYKkVHG1hcmMuenlu Z2llckBhcm0uY29tAAoJECPQ0LrRPXpDJ+MQAKIoE5YA5AydC64kAyQyuKcPb5S4 N/9R/9DoPDbYLc9SY+1I5ygHGzorq7zx/PWJmamNMjknwk0xhfuBaS5smE/m6H+1 dCmgTM3fknEMd5HfLIwpAp/L1Pmq9KYqMtxounSabduWnVMnIqc+7OGAj5fZE7B1 IPTh8xQQ4HPGR3MBYa/754OIBe8Uprb2KGrZugU2Pz8WPAd9NDdKxM84jCwQ9r58 4TFesdC4iC1J83Qr1JmxiBdGOnfhi3cq7wfmRLnTmBeRlhXqYHuzRxPQmjbKtcWk yzFj3OhSLB2KoV7x4nXaaIcKrwETJCj+GThlK8/ZRZ7lu0irBnmBNomFm4RwwRV4 MkqItMqvNAwd+enq0LMAxBScUt/3EEYUJxV6xA6RBfluKPlZMlcyfGi+pS72fNho 0SiKSzokaiTt/XLBfT1s0NI1ASkdPD5Xqo7yAzxDN4O8SzLY71bkFLrQB3ErL/gr 50FYOsRv24e9a6NrSmtw/7z1Os6mY6QEB6lcSi7A0/+MmudU6Kk0mTk5fRf92+rl vqcB7bkkZrMSSsFPJkrBqoPZ+O9R6yqZudt29+n2G9BNWMea/oOCWnz6oYZh0HvX DdE3YQUQBJj2ZGc0CG8XlWY94sJLsS8n99rLxXDkAJ7aQU0uT4g8hbxJG0nDXJfu d7J2FO7LTtaW4JKo =QFqN -----END PGP SIGNATURE----- Merge tag 'irqchip-4.16' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core Pull irqchip updates for 4.16 from Marc Zyngier - Fix a GICv3 issue when parsing ACPI entries for disabled CPUs - Driver for the MIPS Goldfish virtual platform - Small fixlet for the ompic driver - Interrupt polarity support for the Raspberry Pi irqchip
This commit is contained in:
Thomas Gleixner
commit
80023aea83
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@ -12,7 +12,7 @@ Required properties:
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registers
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- interrupt-controller: Identifies the node as an interrupt controller
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- #interrupt-cells: Specifies the number of cells needed to encode an
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interrupt source. The value shall be 1
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interrupt source. The value shall be 2
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Please refer to interrupts.txt in this directory for details of the common
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Interrupt Controllers bindings used by client devices.
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@ -32,6 +32,6 @@ local_intc: local_intc {
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compatible = "brcm,bcm2836-l1-intc";
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reg = <0x40000000 0x100>;
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interrupt-controller;
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#interrupt-cells = <1>;
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#interrupt-cells = <2>;
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interrupt-parent = <&local_intc>;
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};
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@ -0,0 +1,30 @@
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Android Goldfish PIC
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Android Goldfish programmable interrupt device used by Android
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emulator.
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Required properties:
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- compatible : should contain "google,goldfish-pic"
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- reg : <registers mapping>
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- interrupts : <interrupt mapping>
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Example for mips when used in cascade mode:
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cpuintc {
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#interrupt-cells = <0x1>;
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#address-cells = <0>;
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interrupt-controller;
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compatible = "mti,cpu-interrupt-controller";
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};
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interrupt-controller@1f000000 {
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compatible = "google,goldfish-pic";
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reg = <0x1f000000 0x1000>;
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interrupt-controller;
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#interrupt-cells = <0x1>;
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interrupt-parent = <&cpuintc>;
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interrupts = <0x2>;
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};
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@ -867,6 +867,12 @@ S: Supported
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F: drivers/android/
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F: drivers/staging/android/
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ANDROID GOLDFISH PIC DRIVER
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M: Miodrag Dinic <miodrag.dinic@mips.com>
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S: Supported
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F: Documentation/devicetree/bindings/interrupt-controller/google,goldfish-pic.txt
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F: drivers/irqchip/irq-goldfish-pic.c
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ANDROID GOLDFISH RTC DRIVER
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M: Miodrag Dinic <miodrag.dinic@mips.com>
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S: Supported
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@ -13,24 +13,24 @@
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compatible = "brcm,bcm2836-l1-intc";
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reg = <0x40000000 0x100>;
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interrupt-controller;
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#interrupt-cells = <1>;
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#interrupt-cells = <2>;
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interrupt-parent = <&local_intc>;
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};
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arm-pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupt-parent = <&local_intc>;
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interrupts = <9>;
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interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupt-parent = <&local_intc>;
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interrupts = <0>, // PHYS_SECURE_PPI
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<1>, // PHYS_NONSECURE_PPI
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<3>, // VIRT_PPI
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<2>; // HYP_PPI
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interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI
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<1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI
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<3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI
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<2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI
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always-on;
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};
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@ -76,7 +76,7 @@
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compatible = "brcm,bcm2836-armctrl-ic";
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reg = <0x7e00b200 0x200>;
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interrupt-parent = <&local_intc>;
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interrupts = <8>;
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interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
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};
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&cpu_thermal {
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@ -12,7 +12,7 @@
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compatible = "brcm,bcm2836-l1-intc";
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reg = <0x40000000 0x100>;
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interrupt-controller;
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#interrupt-cells = <1>;
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#interrupt-cells = <2>;
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interrupt-parent = <&local_intc>;
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};
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};
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@ -20,10 +20,10 @@
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timer {
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compatible = "arm,armv7-timer";
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interrupt-parent = <&local_intc>;
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interrupts = <0>, // PHYS_SECURE_PPI
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<1>, // PHYS_NONSECURE_PPI
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<3>, // VIRT_PPI
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<2>; // HYP_PPI
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interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI
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<1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI
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<3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI
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<2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI
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always-on;
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};
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@ -73,7 +73,7 @@
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compatible = "brcm,bcm2836-armctrl-ic";
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reg = <0x7e00b200 0x200>;
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interrupt-parent = <&local_intc>;
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interrupts = <8>;
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interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
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};
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&cpu_thermal {
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@ -2,6 +2,7 @@
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#include <dt-bindings/clock/bcm2835.h>
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#include <dt-bindings/clock/bcm2835-aux.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/* firmware-provided startup stubs live here, where the secondary CPUs are
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* spinning.
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@ -343,4 +343,12 @@ config MESON_IRQ_GPIO
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help
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Support Meson SoC Family GPIO Interrupt Multiplexer
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config GOLDFISH_PIC
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bool "Goldfish programmable interrupt controller"
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depends on MIPS && (GOLDFISH || COMPILE_TEST)
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select IRQ_DOMAIN
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help
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Say yes here to enable Goldfish interrupt controller driver used
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for Goldfish based virtual platforms.
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endmenu
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@ -84,3 +84,4 @@ obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o
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obj-$(CONFIG_IRQ_UNIPHIER_AIDET) += irq-uniphier-aidet.o
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obj-$(CONFIG_ARCH_SYNQUACER) += irq-sni-exiu.o
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obj-$(CONFIG_MESON_IRQ_GPIO) += irq-meson-gpio.o
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obj-$(CONFIG_GOLDFISH_PIC) += irq-goldfish-pic.o
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@ -98,13 +98,35 @@ static struct irq_chip bcm2836_arm_irqchip_gpu = {
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.irq_unmask = bcm2836_arm_irqchip_unmask_gpu_irq,
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};
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static void bcm2836_arm_irqchip_register_irq(int hwirq, struct irq_chip *chip)
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static int bcm2836_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hw)
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{
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int irq = irq_create_mapping(intc.domain, hwirq);
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struct irq_chip *chip;
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switch (hw) {
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case LOCAL_IRQ_CNTPSIRQ:
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case LOCAL_IRQ_CNTPNSIRQ:
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case LOCAL_IRQ_CNTHPIRQ:
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case LOCAL_IRQ_CNTVIRQ:
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chip = &bcm2836_arm_irqchip_timer;
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break;
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case LOCAL_IRQ_GPU_FAST:
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chip = &bcm2836_arm_irqchip_gpu;
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break;
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case LOCAL_IRQ_PMU_FAST:
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chip = &bcm2836_arm_irqchip_pmu;
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break;
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default:
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pr_warn_once("Unexpected hw irq: %lu\n", hw);
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return -EINVAL;
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}
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irq_set_percpu_devid(irq);
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irq_set_chip_and_handler(irq, chip, handle_percpu_devid_irq);
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irq_domain_set_info(d, irq, hw, chip, d->host_data,
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handle_percpu_devid_irq, NULL, NULL);
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irq_set_status_flags(irq, IRQ_NOAUTOEN);
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return 0;
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}
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static void
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@ -165,7 +187,8 @@ static int bcm2836_cpu_dying(unsigned int cpu)
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#endif
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static const struct irq_domain_ops bcm2836_arm_irqchip_intc_ops = {
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.xlate = irq_domain_xlate_onecell
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.xlate = irq_domain_xlate_onetwocell,
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.map = bcm2836_map,
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};
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static void
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@ -218,19 +241,6 @@ static int __init bcm2836_arm_irqchip_l1_intc_of_init(struct device_node *node,
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if (!intc.domain)
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panic("%pOF: unable to create IRQ domain\n", node);
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bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_CNTPSIRQ,
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&bcm2836_arm_irqchip_timer);
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bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_CNTPNSIRQ,
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&bcm2836_arm_irqchip_timer);
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bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_CNTHPIRQ,
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&bcm2836_arm_irqchip_timer);
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bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_CNTVIRQ,
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&bcm2836_arm_irqchip_timer);
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bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_GPU_FAST,
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&bcm2836_arm_irqchip_gpu);
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bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_PMU_FAST,
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&bcm2836_arm_irqchip_pmu);
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bcm2836_arm_irqchip_smp_init();
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set_handle_irq(bcm2836_arm_irqchip_handle_irq);
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@ -1331,6 +1331,10 @@ gic_acpi_parse_madt_gicc(struct acpi_subtable_header *header,
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u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2;
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void __iomem *redist_base;
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/* GICC entry which has !ACPI_MADT_ENABLED is not unusable so skip */
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if (!(gicc->flags & ACPI_MADT_ENABLED))
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return 0;
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redist_base = ioremap(gicc->gicr_base_address, size);
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if (!redist_base)
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return -ENOMEM;
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@ -1380,6 +1384,13 @@ static int __init gic_acpi_match_gicc(struct acpi_subtable_header *header,
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if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address)
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return 0;
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/*
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* It's perfectly valid firmware can pass disabled GICC entry, driver
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* should not treat as errors, skip the entry instead of probe fail.
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*/
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if (!(gicc->flags & ACPI_MADT_ENABLED))
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return 0;
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return -ENODEV;
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}
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|
|
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@ -0,0 +1,139 @@
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/*
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* Driver for MIPS Goldfish Programmable Interrupt Controller.
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*
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* Author: Miodrag Dinic <miodrag.dinic@mips.com>
|
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*
|
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* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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|
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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|
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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||||
#include <linux/irqchip.h>
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#include <linux/irqchip/chained_irq.h>
|
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#include <linux/irqdomain.h>
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||||
#include <linux/of_address.h>
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||||
#include <linux/of_irq.h>
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||||
|
||||
#define GFPIC_NR_IRQS 32
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|
||||
/* 8..39 Cascaded Goldfish PIC interrupts */
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||||
#define GFPIC_IRQ_BASE 8
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||||
|
||||
#define GFPIC_REG_IRQ_PENDING 0x04
|
||||
#define GFPIC_REG_IRQ_DISABLE_ALL 0x08
|
||||
#define GFPIC_REG_IRQ_DISABLE 0x0c
|
||||
#define GFPIC_REG_IRQ_ENABLE 0x10
|
||||
|
||||
struct goldfish_pic_data {
|
||||
void __iomem *base;
|
||||
struct irq_domain *irq_domain;
|
||||
};
|
||||
|
||||
static void goldfish_pic_cascade(struct irq_desc *desc)
|
||||
{
|
||||
struct goldfish_pic_data *gfpic = irq_desc_get_handler_data(desc);
|
||||
struct irq_chip *host_chip = irq_desc_get_chip(desc);
|
||||
u32 pending, hwirq, virq;
|
||||
|
||||
chained_irq_enter(host_chip, desc);
|
||||
|
||||
pending = readl(gfpic->base + GFPIC_REG_IRQ_PENDING);
|
||||
while (pending) {
|
||||
hwirq = __fls(pending);
|
||||
virq = irq_linear_revmap(gfpic->irq_domain, hwirq);
|
||||
generic_handle_irq(virq);
|
||||
pending &= ~(1 << hwirq);
|
||||
}
|
||||
|
||||
chained_irq_exit(host_chip, desc);
|
||||
}
|
||||
|
||||
static const struct irq_domain_ops goldfish_irq_domain_ops = {
|
||||
.xlate = irq_domain_xlate_onecell,
|
||||
};
|
||||
|
||||
static int __init goldfish_pic_of_init(struct device_node *of_node,
|
||||
struct device_node *parent)
|
||||
{
|
||||
struct goldfish_pic_data *gfpic;
|
||||
struct irq_chip_generic *gc;
|
||||
struct irq_chip_type *ct;
|
||||
unsigned int parent_irq;
|
||||
int ret = 0;
|
||||
|
||||
gfpic = kzalloc(sizeof(*gfpic), GFP_KERNEL);
|
||||
if (!gfpic) {
|
||||
ret = -ENOMEM;
|
||||
goto out_err;
|
||||
}
|
||||
|
||||
parent_irq = irq_of_parse_and_map(of_node, 0);
|
||||
if (!parent_irq) {
|
||||
pr_err("Failed to map parent IRQ!\n");
|
||||
ret = -EINVAL;
|
||||
goto out_free;
|
||||
}
|
||||
|
||||
gfpic->base = of_iomap(of_node, 0);
|
||||
if (!gfpic->base) {
|
||||
pr_err("Failed to map base address!\n");
|
||||
ret = -ENOMEM;
|
||||
goto out_unmap_irq;
|
||||
}
|
||||
|
||||
/* Mask interrupts. */
|
||||
writel(1, gfpic->base + GFPIC_REG_IRQ_DISABLE_ALL);
|
||||
|
||||
gc = irq_alloc_generic_chip("GFPIC", 1, GFPIC_IRQ_BASE, gfpic->base,
|
||||
handle_level_irq);
|
||||
if (!gc) {
|
||||
pr_err("Failed to allocate chip structures!\n");
|
||||
ret = -ENOMEM;
|
||||
goto out_iounmap;
|
||||
}
|
||||
|
||||
ct = gc->chip_types;
|
||||
ct->regs.enable = GFPIC_REG_IRQ_ENABLE;
|
||||
ct->regs.disable = GFPIC_REG_IRQ_DISABLE;
|
||||
ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
|
||||
ct->chip.irq_mask = irq_gc_mask_disable_reg;
|
||||
|
||||
irq_setup_generic_chip(gc, IRQ_MSK(GFPIC_NR_IRQS), 0,
|
||||
IRQ_NOPROBE | IRQ_LEVEL, 0);
|
||||
|
||||
gfpic->irq_domain = irq_domain_add_legacy(of_node, GFPIC_NR_IRQS,
|
||||
GFPIC_IRQ_BASE, 0,
|
||||
&goldfish_irq_domain_ops,
|
||||
NULL);
|
||||
if (!gfpic->irq_domain) {
|
||||
pr_err("Failed to add irqdomain!\n");
|
||||
ret = -ENOMEM;
|
||||
goto out_destroy_generic_chip;
|
||||
}
|
||||
|
||||
irq_set_chained_handler_and_data(parent_irq,
|
||||
goldfish_pic_cascade, gfpic);
|
||||
|
||||
pr_info("Successfully registered.\n");
|
||||
return 0;
|
||||
|
||||
out_destroy_generic_chip:
|
||||
irq_destroy_generic_chip(gc, IRQ_MSK(GFPIC_NR_IRQS),
|
||||
IRQ_NOPROBE | IRQ_LEVEL, 0);
|
||||
out_iounmap:
|
||||
iounmap(gfpic->base);
|
||||
out_unmap_irq:
|
||||
irq_dispose_mapping(parent_irq);
|
||||
out_free:
|
||||
kfree(gfpic);
|
||||
out_err:
|
||||
pr_err("Failed to initialize! (errno = %d)\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
IRQCHIP_DECLARE(google_gf_pic, "google,goldfish-pic", goldfish_pic_of_init);
|
||||
|
|
@ -171,9 +171,9 @@ static int __init ompic_of_init(struct device_node *node,
|
|||
|
||||
/* Setup the device */
|
||||
ompic_base = ioremap(res.start, resource_size(&res));
|
||||
if (IS_ERR(ompic_base)) {
|
||||
if (!ompic_base) {
|
||||
pr_err("ompic: unable to map registers");
|
||||
return PTR_ERR(ompic_base);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
irq = irq_of_parse_and_map(node, 0);
|
||||
|
|
|
|||
Loading…
Reference in New Issue