ARM: OMAP: Fix DMA channel irq handling for omap24xx
- DMA CSR register is cleared by reading on omap1, but on omap2 it is cleard by writing to it. - DMA TOUT interrupt does not exist on omap24xx, rename it - Add SECURE and MISALIGNED errors by default for omap24xx - Add defines for external DMA request lines Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Tony Lindgren
parent
6dc3c8f201
commit
7ff879dbcd
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@ -43,6 +43,7 @@
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#define OMAP_DMA_ACTIVE 0x01
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#define OMAP_DMA_CCR_EN (1 << 7)
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#define OMAP2_DMA_CSR_CLEAR_MASK 0xffe
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#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
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@ -409,8 +410,11 @@ static inline void omap_enable_channel_irq(int lch)
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{
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u32 status;
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/* Read CSR to make sure it's cleared. */
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status = OMAP_DMA_CSR_REG(lch);
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/* Clear CSR */
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if (cpu_class_is_omap1())
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status = OMAP_DMA_CSR_REG(lch);
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else if (cpu_is_omap24xx())
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OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK;
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/* Enable some nice interrupts. */
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OMAP_DMA_CICR_REG(lch) = dma_chan[lch].enabled_irqs;
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@ -509,11 +513,13 @@ int omap_request_dma(int dev_id, const char *dev_name,
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chan->dev_name = dev_name;
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chan->callback = callback;
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chan->data = data;
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chan->enabled_irqs = OMAP_DMA_TOUT_IRQ | OMAP_DMA_DROP_IRQ |
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OMAP_DMA_BLOCK_IRQ;
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chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
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if (cpu_is_omap24xx())
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chan->enabled_irqs |= OMAP2_DMA_TRANS_ERR_IRQ;
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if (cpu_class_is_omap1())
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chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
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else if (cpu_is_omap24xx())
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chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
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OMAP2_DMA_TRANS_ERR_IRQ;
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if (cpu_is_omap16xx()) {
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/* If the sync device is set, configure it dynamically. */
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@ -533,7 +539,7 @@ int omap_request_dma(int dev_id, const char *dev_name,
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omap_enable_channel_irq(free_ch);
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/* Clear the CSR register and IRQ status register */
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OMAP_DMA_CSR_REG(free_ch) = 0x0;
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OMAP_DMA_CSR_REG(free_ch) = OMAP2_DMA_CSR_CLEAR_MASK;
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omap_writel(~0x0, OMAP_DMA4_IRQSTATUS_L0);
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}
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@ -573,7 +579,7 @@ void omap_free_dma(int lch)
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omap_writel(val, OMAP_DMA4_IRQENABLE_L0);
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/* Clear the CSR register and IRQ status register */
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OMAP_DMA_CSR_REG(lch) = 0x0;
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OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK;
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val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
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val |= 1 << lch;
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@ -837,7 +843,7 @@ static int omap1_dma_handle_ch(int ch)
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"%d (CSR %04x)\n", ch, csr);
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return 0;
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}
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if (unlikely(csr & OMAP_DMA_TOUT_IRQ))
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if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
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printk(KERN_WARNING "DMA timeout with device %d\n",
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dma_chan[ch].dev_id);
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if (unlikely(csr & OMAP_DMA_DROP_IRQ))
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@ -885,20 +891,21 @@ static int omap2_dma_handle_ch(int ch)
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return 0;
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if (unlikely(dma_chan[ch].dev_id == -1))
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return 0;
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/* REVISIT: According to 24xx TRM, there's no TOUT_IE */
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if (unlikely(status & OMAP_DMA_TOUT_IRQ))
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printk(KERN_INFO "DMA timeout with device %d\n",
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dma_chan[ch].dev_id);
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if (unlikely(status & OMAP_DMA_DROP_IRQ))
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printk(KERN_INFO
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"DMA synchronization event drop occurred with device "
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"%d\n", dma_chan[ch].dev_id);
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if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ))
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printk(KERN_INFO "DMA transaction error with device %d\n",
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dma_chan[ch].dev_id);
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if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
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printk(KERN_INFO "DMA secure error with device %d\n",
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dma_chan[ch].dev_id);
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if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
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printk(KERN_INFO "DMA misaligned error with device %d\n",
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dma_chan[ch].dev_id);
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OMAP_DMA_CSR_REG(ch) = 0x20;
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OMAP_DMA_CSR_REG(ch) = OMAP2_DMA_CSR_CLEAR_MASK;
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val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
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/* ch in this function is from 0-31 while in register it is 1-32 */
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@ -663,7 +663,7 @@ static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
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return;
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}
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/* FIXME: We really should do something to _handle_ the errors */
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if (ch_status & OMAP_DMA_TOUT_IRQ) {
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if (ch_status & OMAP1_DMA_TOUT_IRQ) {
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dev_err(mmc_dev(host->mmc),"DMA timeout\n");
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return;
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}
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@ -773,7 +773,7 @@ static void dma_error(int lch, u16 ch_status, void *data)
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struct omap_ep *ep = data;
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/* if ch_status & OMAP_DMA_DROP_IRQ ... */
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/* if ch_status & OMAP_DMA_TOUT_IRQ ... */
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/* if ch_status & OMAP1_DMA_TOUT_IRQ ... */
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ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
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/* complete current transfer ... */
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@ -185,8 +185,8 @@
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/* DMA channels for 24xx */
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#define OMAP24XX_DMA_NO_DEVICE 0
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#define OMAP24XX_DMA_XTI_DMA 1 /* S_DMA_0 */
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#define OMAP24XX_DMA_EXT_NDMA_REQ0 2 /* S_DMA_1 */
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#define OMAP24XX_DMA_EXT_NDMA_REQ1 3 /* S_DMA_2 */
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#define OMAP24XX_DMA_EXT_DMAREQ0 2 /* S_DMA_1 */
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#define OMAP24XX_DMA_EXT_DMAREQ1 3 /* S_DMA_2 */
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#define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */
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#define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */
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#define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */
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@ -197,7 +197,9 @@
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#define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */
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#define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */
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#define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */
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#define OMAP24XX_DMA_EXT_DMAREQ2 14 /* S_DMA_13 */
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#define OMAP24XX_DMA_EXT_DMAREQ3 15 /* S_DMA_14 */
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#define OMAP24XX_DMA_EXT_DMAREQ4 16 /* S_DMA_15 */
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#define OMAP24XX_DMA_EAC_AC_RD 17 /* S_DMA_16 */
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#define OMAP24XX_DMA_EAC_AC_WR 18 /* S_DMA_17 */
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#define OMAP24XX_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */
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@ -244,6 +246,7 @@
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#define OMAP24XX_DMA_MMC1_TX 61 /* SDMA_60 */
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#define OMAP24XX_DMA_MMC1_RX 62 /* SDMA_61 */
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#define OMAP24XX_DMA_MS 63 /* SDMA_62 */
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#define OMAP24XX_DMA_EXT_DMAREQ5 64 /* S_DMA_63 */
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/*----------------------------------------------------------------------------*/
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@ -274,7 +277,7 @@
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#define OMAP1610_DMA_LCD_LCH_CTRL (OMAP1610_DMA_LCD_BASE + 0xea)
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#define OMAP1610_DMA_LCD_SRC_FI_B1_U (OMAP1610_DMA_LCD_BASE + 0xf4)
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#define OMAP_DMA_TOUT_IRQ (1 << 0) /* Only on omap1 */
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#define OMAP1_DMA_TOUT_IRQ (1 << 0)
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#define OMAP_DMA_DROP_IRQ (1 << 1)
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#define OMAP_DMA_HALF_IRQ (1 << 2)
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#define OMAP_DMA_FRAME_IRQ (1 << 3)
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