arm64: dts: mt8173: Add the mmsys reset bit to reset the dsi0
Reset the DSI hardware is needed to prevent different settings between the bootloader and the kernel. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210930103105.v4.4.I7bd7d9a8da5e2894711b700a1127e6902a2b2f1d@changeid Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
parent
858d8e140c
commit
7fdb1bc3d9
|
@ -996,6 +996,7 @@
|
|||
assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
|
||||
assigned-clock-rates = <400000000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
|
||||
<&gce 1 CMDQ_THR_PRIO_HIGHEST>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
|
||||
|
@ -1222,6 +1223,7 @@
|
|||
<&mmsys CLK_MM_DSI0_DIGITAL>,
|
||||
<&mipi_tx0>;
|
||||
clock-names = "engine", "digital", "hs";
|
||||
resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>;
|
||||
phys = <&mipi_tx0>;
|
||||
phy-names = "dphy";
|
||||
status = "disabled";
|
||||
|
|
|
@ -27,6 +27,8 @@
|
|||
#define MT8173_INFRA_GCE_FAXI_RST 40
|
||||
#define MT8173_INFRA_MMIOMMURST 47
|
||||
|
||||
/* MMSYS resets */
|
||||
#define MT8173_MMSYS_SW0_RST_B_DISP_DSI0 25
|
||||
|
||||
/* PERICFG resets */
|
||||
#define MT8173_PERI_UART0_SW_RST 0
|
||||
|
|
Loading…
Reference in New Issue