xtensa: clean up labels in the kernel entry assembly
Don't use numeric labels for long jumps, use named local labels instead. Avoid conditional label definition. No functional changes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Max Filippov
parent
2a26f4ee39
commit
7f9c974174
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@ -169,28 +169,26 @@ _user_exception:
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/* Save only live registers. */
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UABI_W _bbsi.l a2, 1, 1f
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UABI_W _bbsi.l a2, 1, .Lsave_window_registers
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s32i a4, a1, PT_AREG4
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s32i a5, a1, PT_AREG5
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s32i a6, a1, PT_AREG6
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s32i a7, a1, PT_AREG7
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UABI_W _bbsi.l a2, 2, 1f
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UABI_W _bbsi.l a2, 2, .Lsave_window_registers
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s32i a8, a1, PT_AREG8
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s32i a9, a1, PT_AREG9
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s32i a10, a1, PT_AREG10
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s32i a11, a1, PT_AREG11
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UABI_W _bbsi.l a2, 3, 1f
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UABI_W _bbsi.l a2, 3, .Lsave_window_registers
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s32i a12, a1, PT_AREG12
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s32i a13, a1, PT_AREG13
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s32i a14, a1, PT_AREG14
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s32i a15, a1, PT_AREG15
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#if defined(USER_SUPPORT_WINDOWED)
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_bnei a2, 1, 1f # only one valid frame?
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/* If only one valid frame skip saving regs. */
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/* Only one valid frame, skip saving regs. */
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j 2f
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beqi a2, 1, common_exception
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/* Save the remaining registers.
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* We have to save all registers up to the first '1' from
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@ -199,8 +197,8 @@ UABI_W _bbsi.l a2, 3, 1f
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* All register frames starting from the top field to the marked '1'
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* must be saved.
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*/
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1: addi a3, a2, -1 # eliminate '1' in bit 0: yyyyxxww0
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.Lsave_window_registers:
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addi a3, a2, -1 # eliminate '1' in bit 0: yyyyxxww0
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neg a3, a3 # yyyyxxww0 -> YYYYXXWW1+1
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and a3, a3, a2 # max. only one bit is set
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@ -241,7 +239,7 @@ UABI_W _bbsi.l a2, 3, 1f
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/* We are back to the original stack pointer (a1) */
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#endif
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2: /* Now, jump to the common exception handler. */
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/* Now, jump to the common exception handler. */
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j common_exception
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@ -795,7 +793,7 @@ ENDPROC(kernel_exception)
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ENTRY(debug_exception)
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rsr a0, SREG_EPS + XCHAL_DEBUGLEVEL
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bbsi.l a0, PS_EXCM_BIT, 1f # exception mode
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bbsi.l a0, PS_EXCM_BIT, .Ldebug_exception_in_exception # exception mode
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/* Set EPC1 and EXCCAUSE */
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@ -814,10 +812,10 @@ ENTRY(debug_exception)
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/* Switch to kernel/user stack, restore jump vector, and save a0 */
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bbsi.l a2, PS_UM_BIT, 2f # jump if user mode
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bbsi.l a2, PS_UM_BIT, .Ldebug_exception_user # jump if user mode
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addi a2, a1, -16 - PT_KERNEL_SIZE # assume kernel stack
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3:
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.Ldebug_exception_continue:
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l32i a0, a3, DT_DEBUG_SAVE
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s32i a1, a2, PT_AREG1
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s32i a0, a2, PT_AREG0
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@ -845,10 +843,12 @@ ENTRY(debug_exception)
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bbsi.l a2, PS_UM_BIT, _user_exception
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j _kernel_exception
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2: rsr a2, excsave1
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.Ldebug_exception_user:
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rsr a2, excsave1
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l32i a2, a2, EXC_TABLE_KSTK # load kernel stack pointer
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j 3b
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j .Ldebug_exception_continue
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.Ldebug_exception_in_exception:
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#ifdef CONFIG_HAVE_HW_BREAKPOINT
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/* Debug exception while in exception mode. This may happen when
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* window overflow/underflow handler or fast exception handler hits
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@ -856,8 +856,8 @@ ENTRY(debug_exception)
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* breakpoints, single-step faulting instruction and restore data
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* breakpoints.
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*/
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1:
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bbci.l a0, PS_UM_BIT, 1b # jump if kernel mode
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bbci.l a0, PS_UM_BIT, .Ldebug_exception_in_exception # jump if kernel mode
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rsr a0, debugcause
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bbsi.l a0, DEBUGCAUSE_DBREAK_BIT, .Ldebug_save_dbreak
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@ -901,7 +901,7 @@ ENTRY(debug_exception)
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rfi XCHAL_DEBUGLEVEL
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#else
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/* Debug exception while in exception mode. Should not happen. */
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1: j 1b // FIXME!!
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j .Ldebug_exception_in_exception // FIXME!!
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#endif
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ENDPROC(debug_exception)
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@ -1630,12 +1630,13 @@ ENTRY(fast_second_level_miss)
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GET_CURRENT(a1,a2)
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l32i a0, a1, TASK_MM # tsk->mm
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beqz a0, 9f
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beqz a0, .Lfast_second_level_miss_no_mm
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8: rsr a3, excvaddr # fault address
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.Lfast_second_level_miss_continue:
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rsr a3, excvaddr # fault address
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_PGD_OFFSET(a0, a3, a1)
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l32i a0, a0, 0 # read pmdval
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beqz a0, 2f
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beqz a0, .Lfast_second_level_miss_no_pmd
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/* Read ptevaddr and convert to top of page-table page.
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*
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@ -1678,12 +1679,13 @@ ENTRY(fast_second_level_miss)
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addi a3, a3, DTLB_WAY_PGD
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add a1, a1, a3 # ... + way_number
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3: wdtlb a0, a1
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.Lfast_second_level_miss_wdtlb:
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wdtlb a0, a1
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dsync
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/* Exit critical section. */
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4: rsr a3, excsave1
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.Lfast_second_level_miss_skip_wdtlb:
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rsr a3, excsave1
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movi a0, 0
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s32i a0, a3, EXC_TABLE_FIXUP
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@ -1707,19 +1709,21 @@ ENTRY(fast_second_level_miss)
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esync
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rfde
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9: l32i a0, a1, TASK_ACTIVE_MM # unlikely case mm == 0
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bnez a0, 8b
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.Lfast_second_level_miss_no_mm:
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l32i a0, a1, TASK_ACTIVE_MM # unlikely case mm == 0
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bnez a0, .Lfast_second_level_miss_continue
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/* Even more unlikely case active_mm == 0.
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* We can get here with NMI in the middle of context_switch that
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* touches vmalloc area.
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*/
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movi a0, init_mm
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j 8b
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j .Lfast_second_level_miss_continue
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.Lfast_second_level_miss_no_pmd:
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#if (DCACHE_WAY_SIZE > PAGE_SIZE)
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2: /* Special case for cache aliasing.
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/* Special case for cache aliasing.
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* We (should) only get here if a clear_user_page, copy_user_page
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* or the aliased cache flush functions got preemptively interrupted
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* by another task. Re-establish temporary mapping to the
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@ -1729,24 +1733,24 @@ ENTRY(fast_second_level_miss)
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/* We shouldn't be in a double exception */
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l32i a0, a2, PT_DEPC
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bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, 2f
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bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, .Lfast_second_level_miss_slow
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/* Make sure the exception originated in the special functions */
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movi a0, __tlbtemp_mapping_start
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rsr a3, epc1
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bltu a3, a0, 2f
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bltu a3, a0, .Lfast_second_level_miss_slow
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movi a0, __tlbtemp_mapping_end
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bgeu a3, a0, 2f
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bgeu a3, a0, .Lfast_second_level_miss_slow
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/* Check if excvaddr was in one of the TLBTEMP_BASE areas. */
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movi a3, TLBTEMP_BASE_1
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rsr a0, excvaddr
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bltu a0, a3, 2f
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bltu a0, a3, .Lfast_second_level_miss_slow
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addi a1, a0, -TLBTEMP_SIZE
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bgeu a1, a3, 2f
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bgeu a1, a3, .Lfast_second_level_miss_slow
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/* Check if we have to restore an ITLB mapping. */
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@ -1772,19 +1776,19 @@ ENTRY(fast_second_level_miss)
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mov a0, a6
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movnez a0, a7, a3
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j 3b
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j .Lfast_second_level_miss_wdtlb
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/* ITLB entry. We only use dst in a6. */
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1: witlb a6, a1
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isync
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j 4b
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j .Lfast_second_level_miss_skip_wdtlb
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#endif // DCACHE_WAY_SIZE > PAGE_SIZE
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2: /* Invalid PGD, default exception handling */
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/* Invalid PGD, default exception handling */
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.Lfast_second_level_miss_slow:
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rsr a1, depc
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s32i a1, a2, PT_AREG2
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@ -1824,12 +1828,13 @@ ENTRY(fast_store_prohibited)
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GET_CURRENT(a1,a2)
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l32i a0, a1, TASK_MM # tsk->mm
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beqz a0, 9f
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beqz a0, .Lfast_store_no_mm
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8: rsr a1, excvaddr # fault address
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.Lfast_store_continue:
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rsr a1, excvaddr # fault address
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_PGD_OFFSET(a0, a1, a3)
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l32i a0, a0, 0
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beqz a0, 2f
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beqz a0, .Lfast_store_slow
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/*
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* Note that we test _PAGE_WRITABLE_BIT only if PTE is present
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@ -1839,8 +1844,8 @@ ENTRY(fast_store_prohibited)
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_PTE_OFFSET(a0, a1, a3)
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l32i a3, a0, 0 # read pteval
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movi a1, _PAGE_CA_INVALID
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ball a3, a1, 2f
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bbci.l a3, _PAGE_WRITABLE_BIT, 2f
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ball a3, a1, .Lfast_store_slow
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bbci.l a3, _PAGE_WRITABLE_BIT, .Lfast_store_slow
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movi a1, _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_HW_WRITE
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or a3, a3, a1
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@ -1868,7 +1873,6 @@ ENTRY(fast_store_prohibited)
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l32i a2, a2, PT_DEPC
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bgeui a2, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f
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rsr a2, depc
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rfe
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@ -1878,10 +1882,12 @@ ENTRY(fast_store_prohibited)
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esync
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rfde
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9: l32i a0, a1, TASK_ACTIVE_MM # unlikely case mm == 0
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j 8b
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.Lfast_store_no_mm:
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l32i a0, a1, TASK_ACTIVE_MM # unlikely case mm == 0
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j .Lfast_store_continue
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2: /* If there was a problem, handle fault in C */
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/* If there was a problem, handle fault in C */
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.Lfast_store_slow:
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rsr a1, excvaddr
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pdtlb a0, a1
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bbci.l a0, DTLB_HIT_BIT, 1f
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