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ath10k: Get rid of "per_ce_irq" hw param 

As of the patch ("ath10k: Keep track of which interrupts fired, don't
poll them") we now have no users of this hardware parameter.  Remove
it.

Suggested-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Link: https://lore.kernel.org/r/20200709082024.v2.2.I083faa4e62e69f863311c89ae5eb28ec5a229b70@changeid
This commit is contained in:
Douglas Anderson 2020-08-31 18:28:47 +03:00 committed by Kalle Valo
parent d66d24ac30
commit 7f86551665
2 changed files with 0 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
drivers/net/wireless/ath/ath10k/core.c
View File

@ -119,7 +119,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.num_wds_entries = 0x20, .num_wds_entries = 0x20,
.target_64bit = false, .target_64bit = false,
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
.per_ce_irq = false,
.shadow_reg_support = false, .shadow_reg_support = false,
.rri_on_ddr = false, .rri_on_ddr = false,
.hw_filter_reset_required = true, .hw_filter_reset_required = true,
@ -155,7 +154,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.num_wds_entries = 0x20, .num_wds_entries = 0x20,
.target_64bit = false, .target_64bit = false,
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
.per_ce_irq = false,
.shadow_reg_support = false, .shadow_reg_support = false,
.rri_on_ddr = false, .rri_on_ddr = false,
.hw_filter_reset_required = true, .hw_filter_reset_required = true,
@ -220,7 +218,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.num_wds_entries = 0x20, .num_wds_entries = 0x20,
.target_64bit = false, .target_64bit = false,
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
.per_ce_irq = false,
.shadow_reg_support = false, .shadow_reg_support = false,
.rri_on_ddr = false, .rri_on_ddr = false,
.hw_filter_reset_required = true, .hw_filter_reset_required = true,
@ -255,7 +252,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.num_wds_entries = 0x20, .num_wds_entries = 0x20,
.target_64bit = false, .target_64bit = false,
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
.per_ce_irq = false,
.shadow_reg_support = false, .shadow_reg_support = false,
.rri_on_ddr = false, .rri_on_ddr = false,
.hw_filter_reset_required = true, .hw_filter_reset_required = true,
@ -290,7 +286,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.num_wds_entries = 0x20, .num_wds_entries = 0x20,
.target_64bit = false, .target_64bit = false,
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
.per_ce_irq = false,
.shadow_reg_support = false, .shadow_reg_support = false,
.rri_on_ddr = false, .rri_on_ddr = false,
.hw_filter_reset_required = true, .hw_filter_reset_required = true,
@ -328,7 +323,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.num_wds_entries = 0x20, .num_wds_entries = 0x20,
.target_64bit = false, .target_64bit = false,
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
.per_ce_irq = false,
.shadow_reg_support = false, .shadow_reg_support = false,
.rri_on_ddr = false, .rri_on_ddr = false,
.hw_filter_reset_required = true, .hw_filter_reset_required = true,
@ -370,7 +364,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.num_wds_entries = 0x20, .num_wds_entries = 0x20,
.target_64bit = false, .target_64bit = false,
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
.per_ce_irq = false,
.shadow_reg_support = false, .shadow_reg_support = false,
.rri_on_ddr = false, .rri_on_ddr = false,
.hw_filter_reset_required = true, .hw_filter_reset_required = true,
@ -418,7 +411,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.num_wds_entries = 0x20, .num_wds_entries = 0x20,
.target_64bit = false, .target_64bit = false,
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
.per_ce_irq = false,
.shadow_reg_support = false, .shadow_reg_support = false,
.rri_on_ddr = false, .rri_on_ddr = false,
.hw_filter_reset_required = true, .hw_filter_reset_required = true,
@ -463,7 +455,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.num_wds_entries = 0x20, .num_wds_entries = 0x20,
.target_64bit = false, .target_64bit = false,
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
.per_ce_irq = false,
.shadow_reg_support = false, .shadow_reg_support = false,
.rri_on_ddr = false, .rri_on_ddr = false,
.hw_filter_reset_required = true, .hw_filter_reset_required = true,
@ -498,7 +489,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.num_wds_entries = 0x20, .num_wds_entries = 0x20,
.target_64bit = false, .target_64bit = false,
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
.per_ce_irq = false,
.shadow_reg_support = false, .shadow_reg_support = false,
.rri_on_ddr = false, .rri_on_ddr = false,
.hw_filter_reset_required = true, .hw_filter_reset_required = true,
@ -535,7 +525,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.num_wds_entries = 0x20, .num_wds_entries = 0x20,
.target_64bit = false, .target_64bit = false,
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
.per_ce_irq = false,
.shadow_reg_support = false, .shadow_reg_support = false,
.rri_on_ddr = false, .rri_on_ddr = false,
.hw_filter_reset_required = true, .hw_filter_reset_required = true,
@ -604,7 +593,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.num_wds_entries = 0x20, .num_wds_entries = 0x20,
.target_64bit = false, .target_64bit = false,
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
.per_ce_irq = false,
.shadow_reg_support = false, .shadow_reg_support = false,
.rri_on_ddr = false, .rri_on_ddr = false,
.hw_filter_reset_required = true, .hw_filter_reset_required = true,
@ -632,7 +620,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.num_wds_entries = TARGET_HL_TLV_NUM_WDS_ENTRIES, .num_wds_entries = TARGET_HL_TLV_NUM_WDS_ENTRIES,
.target_64bit = true, .target_64bit = true,
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL_DUAL_MAC, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL_DUAL_MAC,
.per_ce_irq = true,
.shadow_reg_support = true, .shadow_reg_support = true,
.rri_on_ddr = true, .rri_on_ddr = true,
.hw_filter_reset_required = false, .hw_filter_reset_required = false,

3
drivers/net/wireless/ath/ath10k/hw.h
View File

@ -593,9 +593,6 @@ struct ath10k_hw_params {
/* Target rx ring fill level */ /* Target rx ring fill level */
u32 rx_ring_fill_level; u32 rx_ring_fill_level;
/* target supporting per ce IRQ */
bool per_ce_irq;
/* target supporting shadow register for ce write */ /* target supporting shadow register for ce write */
bool shadow_reg_support; bool shadow_reg_support;