drm/amd/display: Remove Unused Registers
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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fb625e1b65
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@ -717,22 +717,5 @@ static void dsc_write_to_registers(struct display_stream_compressor *dsc, const
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RANGE_MAX_QP14, reg_vals->pps.rc_range_params[14].range_max_qp,
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RANGE_BPG_OFFSET14, reg_vals->pps.rc_range_params[14].range_bpg_offset);
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if (IS_FPGA_MAXIMUS_DC(dsc20->base.ctx->dce_environment)) {
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/* It's safe to do this as long as debug bus is not being used in DAL Diag environment.
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*
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* This is because DSCC_PPS_CONFIG4.INITIAL_DEC_DELAY is a read-only register field (because it's a decoder
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* value not required by DSC encoder). However, since decoding fails when this value is missing from PPS, it's
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* required to communicate this value to the PPS header. When testing on FPGA, the values for PPS header are
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* being read from Diag register dump. The register below is used in place of a scratch register to make
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* 'initial_dec_delay' available.
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*/
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temp_int = reg_vals->pps.initial_dec_delay;
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REG_SET_4(DSCC_TEST_DEBUG_BUS_ROTATE, 0,
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DSCC_TEST_DEBUG_BUS0_ROTATE, temp_int & 0x1f,
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DSCC_TEST_DEBUG_BUS1_ROTATE, temp_int >> 5 & 0x1f,
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DSCC_TEST_DEBUG_BUS2_ROTATE, temp_int >> 10 & 0x1f,
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DSCC_TEST_DEBUG_BUS3_ROTATE, temp_int >> 15 & 0x1);
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}
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}
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@ -78,7 +78,6 @@
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SRI(DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, DSCC, id),\
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SRI(DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, DSCC, id),\
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SRI(DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, DSCC, id),\
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SRI(DSCC_TEST_DEBUG_BUS_ROTATE, DSCC, id),\
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SRI(DSCCIF_CONFIG0, DSCCIF, id),\
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SRI(DSCCIF_CONFIG1, DSCCIF, id),\
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SRI(DSCRM_DSC_FORWARD_CONFIG, DSCRM, id)
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@ -95,8 +94,6 @@
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DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_CLOCK_EN, mask_sh), \
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DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_DISPCLK_R_GATE_DIS, mask_sh), \
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DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_DSCCLK_R_GATE_DIS, mask_sh), \
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DSC_SF(DSC_TOP0_DSC_DEBUG_CONTROL, DSC_DBG_EN, mask_sh), \
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DSC_SF(DSC_TOP0_DSC_DEBUG_CONTROL, DSC_TEST_CLOCK_MUX_SEL, mask_sh), \
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DSC_SF(DSCC0_DSCC_CONFIG0, ICH_RESET_AT_END_OF_LINE, mask_sh), \
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DSC_SF(DSCC0_DSCC_CONFIG0, NUMBER_OF_SLICES_PER_LINE, mask_sh), \
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DSC_SF(DSCC0_DSCC_CONFIG0, ALTERNATE_ICH_ENCODING_EN, mask_sh), \
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@ -249,10 +246,6 @@
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DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, mask_sh), \
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DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, mask_sh), \
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DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, mask_sh), \
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DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS0_ROTATE, mask_sh), \
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DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS1_ROTATE, mask_sh), \
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DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS2_ROTATE, mask_sh), \
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DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS3_ROTATE, mask_sh), \
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DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN, mask_sh), \
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DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \
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DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS, mask_sh), \
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@ -427,10 +420,6 @@
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type DSCC_UPDATE_PENDING_STATUS; \
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type DSCC_UPDATE_TAKEN_STATUS; \
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type DSCC_UPDATE_TAKEN_ACK; \
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type DSCC_TEST_DEBUG_BUS0_ROTATE; \
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type DSCC_TEST_DEBUG_BUS1_ROTATE; \
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type DSCC_TEST_DEBUG_BUS2_ROTATE; \
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type DSCC_TEST_DEBUG_BUS3_ROTATE; \
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type DSCC_RATE_BUFFER0_FULLNESS_LEVEL; \
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type DSCC_RATE_BUFFER1_FULLNESS_LEVEL; \
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type DSCC_RATE_BUFFER2_FULLNESS_LEVEL; \
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@ -503,7 +492,6 @@ struct dcn20_dsc_registers {
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uint32_t DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL;
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uint32_t DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL;
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uint32_t DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL;
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uint32_t DSCC_TEST_DEBUG_BUS_ROTATE;
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uint32_t DSCCIF_CONFIG0;
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uint32_t DSCCIF_CONFIG1;
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uint32_t DSCRM_DSC_FORWARD_CONFIG;
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@ -147,8 +147,7 @@
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LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_DATA_SWAP, mask_sh),\
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LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_DATA_ORDER_INVERT, mask_sh),\
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LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_FIFO_EN, mask_sh),\
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LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_FIFO_RD_START_DELAY, mask_sh),\
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LE_SF(DPCSTX0_DPCSTX_DEBUG_CONFIG, DPCS_DBG_CBUS_DIS, mask_sh)
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LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_FIFO_RD_START_DELAY, mask_sh)
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#define DPCS_DCN2_MASK_SH_LIST(mask_sh)\
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DPCS_MASK_SH_LIST(mask_sh),\
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