drm/i915: sprite support for ValleyView v4
No constant alpha yet though, that needs a new ioctl and/or property to
get/set.
v2: use drm_plane_format_cpp (Ville)
fix up vlv_disable_plane, remove IVB bits (Ville)
remove error path rework (Ville)
fix component order confusion (Ville)
clean up platform init (Ville)
use compute_offset_xtiled (Ville)
v3: fix up more format confusion (Ville)
update to new page offset function (Ville)
v4: remove incorrect formats from framebuffer_init (Ville)
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Jesse Barnes
Daniel Vetter
parent
22f9fe5059
commit
7f1f3851fe
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@ -1630,6 +1630,10 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
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mutex_init(&dev_priv->rps.hw_lock);
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mutex_init(&dev_priv->modeset_restore_lock);
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dev_priv->num_plane = 1;
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if (IS_VALLEYVIEW(dev))
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dev_priv->num_plane = 2;
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ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
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if (ret)
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goto out_gem_unload;
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@ -926,6 +926,7 @@ typedef struct drm_i915_private {
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bool enable_hotplug_processing;
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int num_pch_pll;
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int num_plane;
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unsigned long cfb_size;
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unsigned int cfb_fb;
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@ -3288,6 +3288,63 @@
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#define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
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#define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
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#define _SPACNTR 0x72180
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#define SP_ENABLE (1<<31)
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#define SP_GEAMMA_ENABLE (1<<30)
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#define SP_PIXFORMAT_MASK (0xf<<26)
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#define SP_FORMAT_YUV422 (0<<26)
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#define SP_FORMAT_BGR565 (5<<26)
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#define SP_FORMAT_BGRX8888 (6<<26)
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#define SP_FORMAT_BGRA8888 (7<<26)
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#define SP_FORMAT_RGBX1010102 (8<<26)
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#define SP_FORMAT_RGBA1010102 (9<<26)
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#define SP_FORMAT_RGBX8888 (0xe<<26)
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#define SP_FORMAT_RGBA8888 (0xf<<26)
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#define SP_SOURCE_KEY (1<<22)
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#define SP_YUV_BYTE_ORDER_MASK (3<<16)
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#define SP_YUV_ORDER_YUYV (0<<16)
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#define SP_YUV_ORDER_UYVY (1<<16)
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#define SP_YUV_ORDER_YVYU (2<<16)
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#define SP_YUV_ORDER_VYUY (3<<16)
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#define SP_TILED (1<<10)
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#define _SPALINOFF 0x72184
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#define _SPASTRIDE 0x72188
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#define _SPAPOS 0x7218c
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#define _SPASIZE 0x72190
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#define _SPAKEYMINVAL 0x72194
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#define _SPAKEYMSK 0x72198
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#define _SPASURF 0x7219c
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#define _SPAKEYMAXVAL 0x721a0
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#define _SPATILEOFF 0x721a4
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#define _SPACONSTALPHA 0x721a8
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#define _SPAGAMC 0x721f4
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#define _SPBCNTR 0x72280
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#define _SPBLINOFF 0x72284
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#define _SPBSTRIDE 0x72288
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#define _SPBPOS 0x7228c
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#define _SPBSIZE 0x72290
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#define _SPBKEYMINVAL 0x72294
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#define _SPBKEYMSK 0x72298
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#define _SPBSURF 0x7229c
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#define _SPBKEYMAXVAL 0x722a0
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#define _SPBTILEOFF 0x722a4
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#define _SPBCONSTALPHA 0x722a8
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#define _SPBGAMC 0x722f4
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#define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR)
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#define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF)
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#define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE)
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#define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS)
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#define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE)
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#define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL)
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#define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK)
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#define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF)
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#define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL)
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#define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF)
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#define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA)
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#define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC)
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/* VBIOS regs */
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#define VGACNTRL 0x71400
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# define VGA_DISP_DISABLE (1 << 31)
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@ -8867,7 +8867,7 @@ void intel_modeset_init_hw(struct drm_device *dev)
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void intel_modeset_init(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int i, ret;
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int i, j, ret;
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drm_mode_config_init(dev);
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@ -8903,9 +8903,12 @@ void intel_modeset_init(struct drm_device *dev)
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for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
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intel_crtc_init(dev, i);
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ret = intel_plane_init(dev, i);
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if (ret)
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DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
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for (j = 0; j < dev_priv->num_plane; j++) {
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ret = intel_plane_init(dev, i, j);
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if (ret)
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DRM_DEBUG_KMS("pipe %d plane %d init failed: %d\n",
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i, j, ret);
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}
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}
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intel_cpu_pll_init(dev);
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@ -241,6 +241,7 @@ struct intel_crtc {
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struct intel_plane {
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struct drm_plane base;
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int plane;
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enum pipe pipe;
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struct drm_i915_gem_object *obj;
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bool can_scale;
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@ -489,7 +490,7 @@ extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
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extern int intel_edp_target_clock(struct intel_encoder *,
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struct drm_display_mode *mode);
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extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
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extern int intel_plane_init(struct drm_device *dev, enum pipe pipe);
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extern int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
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extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
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enum plane plane);
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@ -36,6 +36,174 @@
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#include <drm/i915_drm.h>
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#include "i915_drv.h"
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static void
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vlv_update_plane(struct drm_plane *dplane, struct drm_framebuffer *fb,
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struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
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unsigned int crtc_w, unsigned int crtc_h,
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uint32_t x, uint32_t y,
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uint32_t src_w, uint32_t src_h)
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{
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struct drm_device *dev = dplane->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_plane *intel_plane = to_intel_plane(dplane);
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int pipe = intel_plane->pipe;
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int plane = intel_plane->plane;
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u32 sprctl;
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unsigned long sprsurf_offset, linear_offset;
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int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
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sprctl = I915_READ(SPCNTR(pipe, plane));
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/* Mask out pixel format bits in case we change it */
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sprctl &= ~SP_PIXFORMAT_MASK;
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sprctl &= ~SP_YUV_BYTE_ORDER_MASK;
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sprctl &= ~SP_TILED;
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switch (fb->pixel_format) {
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case DRM_FORMAT_YUYV:
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sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
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break;
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case DRM_FORMAT_YVYU:
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sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
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break;
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case DRM_FORMAT_UYVY:
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sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
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break;
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case DRM_FORMAT_VYUY:
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sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
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break;
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case DRM_FORMAT_RGB565:
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sprctl |= SP_FORMAT_BGR565;
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break;
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case DRM_FORMAT_XRGB8888:
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sprctl |= SP_FORMAT_BGRX8888;
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break;
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case DRM_FORMAT_ARGB8888:
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sprctl |= SP_FORMAT_BGRA8888;
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break;
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case DRM_FORMAT_XBGR2101010:
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sprctl |= SP_FORMAT_RGBX1010102;
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break;
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case DRM_FORMAT_ABGR2101010:
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sprctl |= SP_FORMAT_RGBA1010102;
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break;
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case DRM_FORMAT_XBGR8888:
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sprctl |= SP_FORMAT_RGBX8888;
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break;
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case DRM_FORMAT_ABGR8888:
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sprctl |= SP_FORMAT_RGBA8888;
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break;
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default:
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/*
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* If we get here one of the upper layers failed to filter
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* out the unsupported plane formats
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*/
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BUG();
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break;
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}
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if (obj->tiling_mode != I915_TILING_NONE)
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sprctl |= SP_TILED;
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sprctl |= SP_ENABLE;
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/* Sizes are 0 based */
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src_w--;
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src_h--;
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crtc_w--;
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crtc_h--;
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intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size);
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I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
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I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
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linear_offset = y * fb->pitches[0] + x * pixel_size;
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sprsurf_offset = intel_gen4_compute_page_offset(&x, &y,
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obj->tiling_mode,
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pixel_size,
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fb->pitches[0]);
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linear_offset -= sprsurf_offset;
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if (obj->tiling_mode != I915_TILING_NONE)
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I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
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else
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I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
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I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
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I915_WRITE(SPCNTR(pipe, plane), sprctl);
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I915_MODIFY_DISPBASE(SPSURF(pipe, plane), obj->gtt_offset +
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sprsurf_offset);
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POSTING_READ(SPSURF(pipe, plane));
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}
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static void
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vlv_disable_plane(struct drm_plane *dplane)
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{
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struct drm_device *dev = dplane->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_plane *intel_plane = to_intel_plane(dplane);
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int pipe = intel_plane->pipe;
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int plane = intel_plane->plane;
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I915_WRITE(SPCNTR(pipe, plane), I915_READ(SPCNTR(pipe, plane)) &
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~SP_ENABLE);
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/* Activate double buffered register update */
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I915_MODIFY_DISPBASE(SPSURF(pipe, plane), 0);
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POSTING_READ(SPSURF(pipe, plane));
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}
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static int
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vlv_update_colorkey(struct drm_plane *dplane,
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struct drm_intel_sprite_colorkey *key)
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{
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struct drm_device *dev = dplane->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_plane *intel_plane = to_intel_plane(dplane);
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int pipe = intel_plane->pipe;
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int plane = intel_plane->plane;
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u32 sprctl;
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if (key->flags & I915_SET_COLORKEY_DESTINATION)
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return -EINVAL;
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I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
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I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
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I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
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sprctl = I915_READ(SPCNTR(pipe, plane));
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sprctl &= ~SP_SOURCE_KEY;
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if (key->flags & I915_SET_COLORKEY_SOURCE)
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sprctl |= SP_SOURCE_KEY;
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I915_WRITE(SPCNTR(pipe, plane), sprctl);
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POSTING_READ(SPKEYMSK(pipe, plane));
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return 0;
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}
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static void
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vlv_get_colorkey(struct drm_plane *dplane,
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struct drm_intel_sprite_colorkey *key)
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{
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struct drm_device *dev = dplane->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_plane *intel_plane = to_intel_plane(dplane);
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int pipe = intel_plane->pipe;
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int plane = intel_plane->plane;
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u32 sprctl;
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key->min_value = I915_READ(SPKEYMINVAL(pipe, plane));
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key->max_value = I915_READ(SPKEYMAXVAL(pipe, plane));
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key->channel_mask = I915_READ(SPKEYMSK(pipe, plane));
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sprctl = I915_READ(SPCNTR(pipe, plane));
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if (sprctl & SP_SOURCE_KEY)
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key->flags = I915_SET_COLORKEY_SOURCE;
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else
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key->flags = I915_SET_COLORKEY_NONE;
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}
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static void
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ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
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struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
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@ -700,8 +868,22 @@ static uint32_t snb_plane_formats[] = {
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DRM_FORMAT_VYUY,
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};
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static uint32_t vlv_plane_formats[] = {
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DRM_FORMAT_RGB565,
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DRM_FORMAT_ABGR8888,
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DRM_FORMAT_ARGB8888,
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DRM_FORMAT_XBGR8888,
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DRM_FORMAT_XRGB8888,
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DRM_FORMAT_XBGR2101010,
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DRM_FORMAT_ABGR2101010,
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DRM_FORMAT_YUYV,
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DRM_FORMAT_YVYU,
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DRM_FORMAT_UYVY,
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DRM_FORMAT_VYUY,
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};
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int
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intel_plane_init(struct drm_device *dev, enum pipe pipe)
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intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
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{
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struct intel_plane *intel_plane;
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unsigned long possible_crtcs;
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@ -740,14 +922,26 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe)
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intel_plane->can_scale = false;
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else
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intel_plane->can_scale = true;
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intel_plane->max_downscale = 2;
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intel_plane->update_plane = ivb_update_plane;
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intel_plane->disable_plane = ivb_disable_plane;
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intel_plane->update_colorkey = ivb_update_colorkey;
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intel_plane->get_colorkey = ivb_get_colorkey;
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plane_formats = snb_plane_formats;
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num_plane_formats = ARRAY_SIZE(snb_plane_formats);
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if (IS_VALLEYVIEW(dev)) {
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intel_plane->max_downscale = 1;
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intel_plane->update_plane = vlv_update_plane;
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intel_plane->disable_plane = vlv_disable_plane;
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intel_plane->update_colorkey = vlv_update_colorkey;
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intel_plane->get_colorkey = vlv_get_colorkey;
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plane_formats = vlv_plane_formats;
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num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
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} else {
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intel_plane->max_downscale = 2;
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intel_plane->update_plane = ivb_update_plane;
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intel_plane->disable_plane = ivb_disable_plane;
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intel_plane->update_colorkey = ivb_update_colorkey;
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intel_plane->get_colorkey = ivb_get_colorkey;
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plane_formats = snb_plane_formats;
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num_plane_formats = ARRAY_SIZE(snb_plane_formats);
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}
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break;
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default:
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@ -756,6 +950,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe)
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}
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intel_plane->pipe = pipe;
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intel_plane->plane = plane;
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possible_crtcs = (1 << pipe);
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ret = drm_plane_init(dev, &intel_plane->base, possible_crtcs,
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&intel_plane_funcs,
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