Merge branch '40GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/next-queue
Jeff Kirsher says:
====================
40GbE Intel Wired LAN Driver Updates 2019-08-22
This series contains updates to i40e driver only.
Arnd Bergmann reduces the stack usage which was causing warnings on
32-bit architectures due to large structure sizes for 2 functions
getting inlined, so use noinline_for_stack to prevent the compilers from
combining the 2 functions.
Mauro S. M. Rodrigues fixes an issue when reading an EEPROM from SFP
modules that comply with SFF-8472 but do not implement the Digital
Diagnostic Monitoring (DDM) interface for i40e.
Huhai found we were not checking the return value for configuring the
transmit ring and continuing with XDP configuration of the transmit
ring.
Beilei fixes an issue of shifting signed 32-bit integers.
Sylwia adds support for "packet drop mode" to the MAC configuration for
admin queue command. This bit controls the behavior when a no-drop
packet is blocking a TC queue. Adds support for persistent LLDP by
checking the LLDP flag and reading the LLDP from the NVM when enabled.
Adrian fixes the "recovery mode" check to take into account which device
we are on, since x710 devices have 4 register values to check for status
and x722 devices only have 2 register values to check.
Piotr Azarewicz bumps the supported firmware API version to 1.9 which
extends the PHY access admin queue command support.
Jake makes sure the traffic class stats for a VEB are reset when the VEB
stats are reset.
Slawomir fixes a NULL pointer dereference where the VSI pointer was not
updated before passing it to the i40e_set_vf_mac() when the VF is in a
reset state, so wait for the reset to complete.
Grzegorz removes the i40e_update_dcb_config() which was not using the
correct NVM reads, so call i40e_init_dcb() in its place to correctly
update the DCB configuration.
Piotr Kwapulinski expands the scope of i40e_set_mac_type() since this is
needed during probe to determine if we are in recovery mode. Fixed the
driver reset path when in recovery mode.
Marcin fixed an issue where we were breaking out of a loop too early
when trying to get the PHY capabilities.
v2: Combined patch 7 & 9 in the original series, since both patches
bumped firmware API version. Also combined patches 12 & 13 in the
original series, since one increased the scope of checking for MAC
and the follow-on patch made use of function within the new scope.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
7ee7f3e844
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@ -610,8 +610,10 @@ i40e_status i40e_init_adminq(struct i40e_hw *hw)
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if (hw->aq.api_maj_ver > 1 ||
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(hw->aq.api_maj_ver == 1 &&
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hw->aq.api_min_ver >= 8))
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hw->aq.api_min_ver >= 8)) {
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hw->flags |= I40E_HW_FLAG_FW_LLDP_PERSISTENT;
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hw->flags |= I40E_HW_FLAG_DROP_MODE;
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}
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if (hw->aq.api_maj_ver > I40E_FW_API_VERSION_MAJOR) {
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ret_code = I40E_ERR_FIRMWARE_API_VERSION;
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@ -11,8 +11,8 @@
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*/
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#define I40E_FW_API_VERSION_MAJOR 0x0001
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#define I40E_FW_API_VERSION_MINOR_X722 0x0008
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#define I40E_FW_API_VERSION_MINOR_X710 0x0008
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#define I40E_FW_API_VERSION_MINOR_X722 0x0009
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#define I40E_FW_API_VERSION_MINOR_X710 0x0009
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#define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \
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I40E_FW_API_VERSION_MINOR_X710 : \
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@ -2051,20 +2051,21 @@ I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
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struct i40e_aq_set_mac_config {
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__le16 max_frame_size;
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u8 params;
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#define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
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#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
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#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
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#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
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#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
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#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
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#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
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#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
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#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
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#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
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#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
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#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
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#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
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#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
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#define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
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#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
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#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
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#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
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#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
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#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
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#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
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#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
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#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
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#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
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#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
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#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
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#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
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#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
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#define I40E_AQ_SET_MAC_CONFIG_DROP_BLOCKING_PACKET_EN 0x80
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u8 tx_timer_priority; /* bitmap */
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__le16 tx_timer_value;
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__le16 fc_refresh_threshold;
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@ -13,7 +13,7 @@
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* This function sets the mac type of the adapter based on the
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* vendor ID and device ID stored in the hw structure.
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**/
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static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
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i40e_status i40e_set_mac_type(struct i40e_hw *hw)
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{
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i40e_status status = 0;
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@ -1577,19 +1577,22 @@ i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
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status = i40e_asq_send_command(hw, &desc, abilities,
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abilities_size, cmd_details);
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if (status)
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break;
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if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) {
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switch (hw->aq.asq_last_status) {
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case I40E_AQ_RC_EIO:
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status = I40E_ERR_UNKNOWN_PHY;
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break;
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} else if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) {
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case I40E_AQ_RC_EAGAIN:
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usleep_range(1000, 2000);
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total_delay++;
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status = I40E_ERR_TIMEOUT;
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break;
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/* also covers I40E_AQ_RC_OK */
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default:
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break;
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}
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} while ((hw->aq.asq_last_status != I40E_AQ_RC_OK) &&
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(total_delay < max_delay));
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} while ((hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) &&
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(total_delay < max_delay));
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if (status)
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return status;
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@ -1643,25 +1646,15 @@ enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
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return status;
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}
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/**
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* i40e_set_fc
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* @hw: pointer to the hw struct
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* @aq_failures: buffer to return AdminQ failure information
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* @atomic_restart: whether to enable atomic link restart
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*
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* Set the requested flow control mode using set_phy_config.
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**/
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enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
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bool atomic_restart)
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static noinline_for_stack enum i40e_status_code
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i40e_set_fc_status(struct i40e_hw *hw,
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struct i40e_aq_get_phy_abilities_resp *abilities,
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bool atomic_restart)
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{
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enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
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struct i40e_aq_get_phy_abilities_resp abilities;
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struct i40e_aq_set_phy_config config;
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enum i40e_status_code status;
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enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
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u8 pause_mask = 0x0;
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*aq_failures = 0x0;
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switch (fc_mode) {
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case I40E_FC_FULL:
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pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
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@ -1677,6 +1670,48 @@ enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
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break;
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}
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memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
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/* clear the old pause settings */
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config.abilities = abilities->abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
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~(I40E_AQ_PHY_FLAG_PAUSE_RX);
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/* set the new abilities */
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config.abilities |= pause_mask;
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/* If the abilities have changed, then set the new config */
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if (config.abilities == abilities->abilities)
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return 0;
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/* Auto restart link so settings take effect */
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if (atomic_restart)
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config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
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/* Copy over all the old settings */
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config.phy_type = abilities->phy_type;
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config.phy_type_ext = abilities->phy_type_ext;
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config.link_speed = abilities->link_speed;
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config.eee_capability = abilities->eee_capability;
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config.eeer = abilities->eeer_val;
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config.low_power_ctrl = abilities->d3_lpan;
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config.fec_config = abilities->fec_cfg_curr_mod_ext_info &
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I40E_AQ_PHY_FEC_CONFIG_MASK;
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return i40e_aq_set_phy_config(hw, &config, NULL);
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}
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/**
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* i40e_set_fc
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* @hw: pointer to the hw struct
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* @aq_failures: buffer to return AdminQ failure information
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* @atomic_restart: whether to enable atomic link restart
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*
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* Set the requested flow control mode using set_phy_config.
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**/
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enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
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bool atomic_restart)
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{
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struct i40e_aq_get_phy_abilities_resp abilities;
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enum i40e_status_code status;
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*aq_failures = 0x0;
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/* Get the current phy config */
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status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
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NULL);
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@ -1685,31 +1720,10 @@ enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
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return status;
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}
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memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
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/* clear the old pause settings */
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config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
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~(I40E_AQ_PHY_FLAG_PAUSE_RX);
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/* set the new abilities */
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config.abilities |= pause_mask;
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/* If the abilities have changed, then set the new config */
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if (config.abilities != abilities.abilities) {
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/* Auto restart link so settings take effect */
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if (atomic_restart)
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config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
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/* Copy over all the old settings */
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config.phy_type = abilities.phy_type;
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config.phy_type_ext = abilities.phy_type_ext;
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config.link_speed = abilities.link_speed;
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config.eee_capability = abilities.eee_capability;
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config.eeer = abilities.eeer_val;
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config.low_power_ctrl = abilities.d3_lpan;
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config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
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I40E_AQ_PHY_FEC_CONFIG_MASK;
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status = i40e_aq_set_phy_config(hw, &config, NULL);
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status = i40e_set_fc_status(hw, &abilities, atomic_restart);
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if (status)
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*aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
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if (status)
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*aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
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}
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/* Update the link info */
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status = i40e_update_link_info(hw);
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if (status) {
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@ -2537,7 +2551,7 @@ i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
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* i40e_updatelink_status - update status of the HW network link
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* @hw: pointer to the hw struct
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**/
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i40e_status i40e_update_link_info(struct i40e_hw *hw)
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noinline_for_stack i40e_status i40e_update_link_info(struct i40e_hw *hw)
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{
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struct i40e_aq_get_phy_abilities_resp abilities;
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i40e_status status = 0;
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|
|
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|
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@ -877,7 +877,23 @@ i40e_status i40e_init_dcb(struct i40e_hw *hw, bool enable_mib_change)
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return I40E_NOT_SUPPORTED;
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|
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/* Read LLDP NVM area */
|
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ret = i40e_read_lldp_cfg(hw, &lldp_cfg);
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if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT) {
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u8 offset = 0;
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if (hw->mac.type == I40E_MAC_XL710)
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offset = I40E_LLDP_CURRENT_STATUS_XL710_OFFSET;
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else if (hw->mac.type == I40E_MAC_X722)
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offset = I40E_LLDP_CURRENT_STATUS_X722_OFFSET;
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else
|
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return I40E_NOT_SUPPORTED;
|
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|
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ret = i40e_read_nvm_module_data(hw,
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I40E_SR_EMP_SR_SETTINGS_PTR,
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offset, 1,
|
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&lldp_cfg.adminstatus);
|
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} else {
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ret = i40e_read_lldp_cfg(hw, &lldp_cfg);
|
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}
|
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if (ret)
|
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return I40E_ERR_NOT_READY;
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|
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|
|
|
|||
|
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@ -30,6 +30,8 @@
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|||
#define I40E_CEE_SUBTYPE_APP_PRI 4
|
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|
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#define I40E_CEE_MAX_FEAT_TYPE 3
|
||||
#define I40E_LLDP_CURRENT_STATUS_XL710_OFFSET 0x2B
|
||||
#define I40E_LLDP_CURRENT_STATUS_X722_OFFSET 0x31
|
||||
/* Defines for LLDP TLV header */
|
||||
#define I40E_LLDP_TLV_LEN_SHIFT 0
|
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#define I40E_LLDP_TLV_LEN_MASK (0x01FF << I40E_LLDP_TLV_LEN_SHIFT)
|
||||
|
|
|
|||
|
|
@ -5137,6 +5137,12 @@ static int i40e_get_module_info(struct net_device *netdev,
|
|||
/* Module is not SFF-8472 compliant */
|
||||
modinfo->type = ETH_MODULE_SFF_8079;
|
||||
modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
|
||||
} else if (!(sff8472_swap & I40E_MODULE_SFF_DDM_IMPLEMENTED)) {
|
||||
/* Module is SFF-8472 compliant but doesn't implement
|
||||
* Digital Diagnostic Monitoring (DDM).
|
||||
*/
|
||||
modinfo->type = ETH_MODULE_SFF_8079;
|
||||
modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
|
||||
} else {
|
||||
modinfo->type = ETH_MODULE_SFF_8472;
|
||||
modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
|
||||
|
|
|
|||
|
|
@ -534,6 +534,10 @@ void i40e_pf_reset_stats(struct i40e_pf *pf)
|
|||
sizeof(pf->veb[i]->stats));
|
||||
memset(&pf->veb[i]->stats_offsets, 0,
|
||||
sizeof(pf->veb[i]->stats_offsets));
|
||||
memset(&pf->veb[i]->tc_stats, 0,
|
||||
sizeof(pf->veb[i]->tc_stats));
|
||||
memset(&pf->veb[i]->tc_stats_offsets, 0,
|
||||
sizeof(pf->veb[i]->tc_stats_offsets));
|
||||
pf->veb[i]->stat_offsets_loaded = false;
|
||||
}
|
||||
}
|
||||
|
|
@ -3364,7 +3368,7 @@ static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
|
|||
for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
|
||||
err = i40e_configure_tx_ring(vsi->tx_rings[i]);
|
||||
|
||||
if (!i40e_enabled_xdp_vsi(vsi))
|
||||
if (err || !i40e_enabled_xdp_vsi(vsi))
|
||||
return err;
|
||||
|
||||
for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
|
||||
|
|
@ -6415,50 +6419,6 @@ static int i40e_resume_port_tx(struct i40e_pf *pf)
|
|||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_update_dcb_config
|
||||
* @hw: pointer to the HW struct
|
||||
* @enable_mib_change: enable MIB change event
|
||||
*
|
||||
* Update DCB configuration from the firmware
|
||||
**/
|
||||
static enum i40e_status_code
|
||||
i40e_update_dcb_config(struct i40e_hw *hw, bool enable_mib_change)
|
||||
{
|
||||
struct i40e_lldp_variables lldp_cfg;
|
||||
i40e_status ret;
|
||||
|
||||
if (!hw->func_caps.dcb)
|
||||
return I40E_NOT_SUPPORTED;
|
||||
|
||||
/* Read LLDP NVM area */
|
||||
ret = i40e_read_lldp_cfg(hw, &lldp_cfg);
|
||||
if (ret)
|
||||
return I40E_ERR_NOT_READY;
|
||||
|
||||
/* Get DCBX status */
|
||||
ret = i40e_get_dcbx_status(hw, &hw->dcbx_status);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Check the DCBX Status */
|
||||
if (hw->dcbx_status == I40E_DCBX_STATUS_DONE ||
|
||||
hw->dcbx_status == I40E_DCBX_STATUS_IN_PROGRESS) {
|
||||
/* Get current DCBX configuration */
|
||||
ret = i40e_get_dcb_config(hw);
|
||||
if (ret)
|
||||
return ret;
|
||||
} else if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
|
||||
return I40E_ERR_NOT_READY;
|
||||
}
|
||||
|
||||
/* Configure the LLDP MIB change event */
|
||||
if (enable_mib_change)
|
||||
ret = i40e_aq_cfg_lldp_mib_change_event(hw, true, NULL);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_init_pf_dcb - Initialize DCB configuration
|
||||
* @pf: PF being configured
|
||||
|
|
@ -6481,7 +6441,7 @@ static int i40e_init_pf_dcb(struct i40e_pf *pf)
|
|||
goto out;
|
||||
}
|
||||
|
||||
err = i40e_update_dcb_config(hw, true);
|
||||
err = i40e_init_dcb(hw, true);
|
||||
if (!err) {
|
||||
/* Device/Function is not DCBX capable */
|
||||
if ((!hw->func_caps.dcb) ||
|
||||
|
|
@ -14578,9 +14538,20 @@ void i40e_set_fec_in_flags(u8 fec_cfg, u32 *flags)
|
|||
**/
|
||||
static bool i40e_check_recovery_mode(struct i40e_pf *pf)
|
||||
{
|
||||
u32 val = rd32(&pf->hw, I40E_GL_FWSTS);
|
||||
u32 val = rd32(&pf->hw, I40E_GL_FWSTS) & I40E_GL_FWSTS_FWS1B_MASK;
|
||||
bool is_recovery_mode = false;
|
||||
|
||||
if (val & I40E_GL_FWSTS_FWS1B_MASK) {
|
||||
if (pf->hw.mac.type == I40E_MAC_XL710)
|
||||
is_recovery_mode =
|
||||
val == I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_CORER_MASK ||
|
||||
val == I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_GLOBR_MASK ||
|
||||
val == I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_TRANSITION_MASK ||
|
||||
val == I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_NVM_MASK;
|
||||
if (pf->hw.mac.type == I40E_MAC_X722)
|
||||
is_recovery_mode =
|
||||
val == I40E_X722_GL_FWSTS_FWS1B_REC_MOD_CORER_MASK ||
|
||||
val == I40E_X722_GL_FWSTS_FWS1B_REC_MOD_GLOBR_MASK;
|
||||
if (is_recovery_mode) {
|
||||
dev_notice(&pf->pdev->dev, "Firmware recovery mode detected. Limiting functionality.\n");
|
||||
dev_notice(&pf->pdev->dev, "Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware recovery mode.\n");
|
||||
set_bit(__I40E_RECOVERY_MODE, pf->state);
|
||||
|
|
@ -14593,6 +14564,51 @@ static bool i40e_check_recovery_mode(struct i40e_pf *pf)
|
|||
return false;
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_pf_loop_reset - perform reset in a loop.
|
||||
* @pf: board private structure
|
||||
*
|
||||
* This function is useful when a NIC is about to enter recovery mode.
|
||||
* When a NIC's internal data structures are corrupted the NIC's
|
||||
* firmware is going to enter recovery mode.
|
||||
* Right after a POR it takes about 7 minutes for firmware to enter
|
||||
* recovery mode. Until that time a NIC is in some kind of intermediate
|
||||
* state. After that time period the NIC almost surely enters
|
||||
* recovery mode. The only way for a driver to detect intermediate
|
||||
* state is to issue a series of pf-resets and check a return value.
|
||||
* If a PF reset returns success then the firmware could be in recovery
|
||||
* mode so the caller of this code needs to check for recovery mode
|
||||
* if this function returns success. There is a little chance that
|
||||
* firmware will hang in intermediate state forever.
|
||||
* Since waiting 7 minutes is quite a lot of time this function waits
|
||||
* 10 seconds and then gives up by returning an error.
|
||||
*
|
||||
* Return 0 on success, negative on failure.
|
||||
**/
|
||||
static i40e_status i40e_pf_loop_reset(struct i40e_pf *pf)
|
||||
{
|
||||
const unsigned short MAX_CNT = 1000;
|
||||
const unsigned short MSECS = 10;
|
||||
struct i40e_hw *hw = &pf->hw;
|
||||
i40e_status ret;
|
||||
int cnt;
|
||||
|
||||
for (cnt = 0; cnt < MAX_CNT; ++cnt) {
|
||||
ret = i40e_pf_reset(hw);
|
||||
if (!ret)
|
||||
break;
|
||||
msleep(MSECS);
|
||||
}
|
||||
|
||||
if (cnt == MAX_CNT) {
|
||||
dev_info(&pf->pdev->dev, "PF reset failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
pf->pfr_count++;
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_init_recovery_mode - initialize subsystems needed in recovery mode
|
||||
* @pf: board private structure
|
||||
|
|
@ -14821,14 +14837,22 @@ static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|||
|
||||
/* Reset here to make sure all is clean and to define PF 'n' */
|
||||
i40e_clear_hw(hw);
|
||||
if (!i40e_check_recovery_mode(pf)) {
|
||||
err = i40e_pf_reset(hw);
|
||||
if (err) {
|
||||
dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
|
||||
goto err_pf_reset;
|
||||
}
|
||||
pf->pfr_count++;
|
||||
|
||||
err = i40e_set_mac_type(hw);
|
||||
if (err) {
|
||||
dev_warn(&pdev->dev, "unidentified MAC or BLANK NVM: %d\n",
|
||||
err);
|
||||
goto err_pf_reset;
|
||||
}
|
||||
|
||||
err = i40e_pf_loop_reset(pf);
|
||||
if (err) {
|
||||
dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
|
||||
goto err_pf_reset;
|
||||
}
|
||||
|
||||
i40e_check_recovery_mode(pf);
|
||||
|
||||
hw->aq.num_arq_entries = I40E_AQ_LEN;
|
||||
hw->aq.num_asq_entries = I40E_AQ_LEN;
|
||||
hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
|
||||
|
|
|
|||
|
|
@ -321,6 +321,77 @@ i40e_status i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,
|
|||
return ret_code;
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_read_nvm_module_data - Reads NVM Buffer to specified memory location
|
||||
* @hw: pointer to the HW structure
|
||||
* @module_ptr: Pointer to module in words with respect to NVM beginning
|
||||
* @offset: offset in words from module start
|
||||
* @words_data_size: Words to read from NVM
|
||||
* @data_ptr: Pointer to memory location where resulting buffer will be stored
|
||||
**/
|
||||
i40e_status i40e_read_nvm_module_data(struct i40e_hw *hw,
|
||||
u8 module_ptr, u16 offset,
|
||||
u16 words_data_size,
|
||||
u16 *data_ptr)
|
||||
{
|
||||
i40e_status status;
|
||||
u16 ptr_value = 0;
|
||||
u32 flat_offset;
|
||||
|
||||
if (module_ptr != 0) {
|
||||
status = i40e_read_nvm_word(hw, module_ptr, &ptr_value);
|
||||
if (status) {
|
||||
i40e_debug(hw, I40E_DEBUG_ALL,
|
||||
"Reading nvm word failed.Error code: %d.\n",
|
||||
status);
|
||||
return I40E_ERR_NVM;
|
||||
}
|
||||
}
|
||||
#define I40E_NVM_INVALID_PTR_VAL 0x7FFF
|
||||
#define I40E_NVM_INVALID_VAL 0xFFFF
|
||||
|
||||
/* Pointer not initialized */
|
||||
if (ptr_value == I40E_NVM_INVALID_PTR_VAL ||
|
||||
ptr_value == I40E_NVM_INVALID_VAL)
|
||||
return I40E_ERR_BAD_PTR;
|
||||
|
||||
/* Check whether the module is in SR mapped area or outside */
|
||||
if (ptr_value & I40E_PTR_TYPE) {
|
||||
/* Pointer points outside of the Shared RAM mapped area */
|
||||
ptr_value &= ~I40E_PTR_TYPE;
|
||||
|
||||
/* PtrValue in 4kB units, need to convert to words */
|
||||
ptr_value /= 2;
|
||||
flat_offset = ((u32)ptr_value * 0x1000) + (u32)offset;
|
||||
status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
|
||||
if (!status) {
|
||||
status = i40e_aq_read_nvm(hw, 0, 2 * flat_offset,
|
||||
2 * words_data_size,
|
||||
data_ptr, true, NULL);
|
||||
i40e_release_nvm(hw);
|
||||
if (status) {
|
||||
i40e_debug(hw, I40E_DEBUG_ALL,
|
||||
"Reading nvm aq failed.Error code: %d.\n",
|
||||
status);
|
||||
return I40E_ERR_NVM;
|
||||
}
|
||||
} else {
|
||||
return I40E_ERR_NVM;
|
||||
}
|
||||
} else {
|
||||
/* Read from the Shadow RAM */
|
||||
status = i40e_read_nvm_buffer(hw, ptr_value + offset,
|
||||
&words_data_size, data_ptr);
|
||||
if (status) {
|
||||
i40e_debug(hw, I40E_DEBUG_ALL,
|
||||
"Reading nvm buffer failed.Error code: %d.\n",
|
||||
status);
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_read_nvm_buffer_srctl - Reads Shadow RAM buffer via SRCTL register
|
||||
* @hw: pointer to the HW structure
|
||||
|
|
@ -429,6 +500,36 @@ static i40e_status __i40e_read_nvm_buffer(struct i40e_hw *hw,
|
|||
return i40e_read_nvm_buffer_srctl(hw, offset, words, data);
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_read_nvm_buffer - Reads Shadow RAM buffer and acquire lock if necessary
|
||||
* @hw: pointer to the HW structure
|
||||
* @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
|
||||
* @words: (in) number of words to read; (out) number of words actually read
|
||||
* @data: words read from the Shadow RAM
|
||||
*
|
||||
* Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
|
||||
* method. The buffer read is preceded by the NVM ownership take
|
||||
* and followed by the release.
|
||||
**/
|
||||
i40e_status i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,
|
||||
u16 *words, u16 *data)
|
||||
{
|
||||
i40e_status ret_code = 0;
|
||||
|
||||
if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) {
|
||||
ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
|
||||
if (!ret_code) {
|
||||
ret_code = i40e_read_nvm_buffer_aq(hw, offset, words,
|
||||
data);
|
||||
i40e_release_nvm(hw);
|
||||
}
|
||||
} else {
|
||||
ret_code = i40e_read_nvm_buffer_srctl(hw, offset, words, data);
|
||||
}
|
||||
|
||||
return ret_code;
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_write_nvm_aq - Writes Shadow RAM.
|
||||
* @hw: pointer to the HW structure.
|
||||
|
|
|
|||
|
|
@ -315,6 +315,12 @@ i40e_status i40e_acquire_nvm(struct i40e_hw *hw,
|
|||
void i40e_release_nvm(struct i40e_hw *hw);
|
||||
i40e_status i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,
|
||||
u16 *data);
|
||||
i40e_status i40e_read_nvm_module_data(struct i40e_hw *hw,
|
||||
u8 module_ptr, u16 offset,
|
||||
u16 words_data_size,
|
||||
u16 *data_ptr);
|
||||
i40e_status i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,
|
||||
u16 *words, u16 *data);
|
||||
i40e_status i40e_update_nvm_checksum(struct i40e_hw *hw);
|
||||
i40e_status i40e_validate_nvm_checksum(struct i40e_hw *hw,
|
||||
u16 *checksum);
|
||||
|
|
@ -326,6 +332,8 @@ void i40e_nvmupd_check_wait_event(struct i40e_hw *hw, u16 opcode,
|
|||
void i40e_nvmupd_clear_wait_state(struct i40e_hw *hw);
|
||||
void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status);
|
||||
|
||||
i40e_status i40e_set_mac_type(struct i40e_hw *hw);
|
||||
|
||||
extern struct i40e_rx_ptype_decoded i40e_ptype_lookup[];
|
||||
|
||||
static inline struct i40e_rx_ptype_decoded decode_rx_desc_ptype(u8 ptype)
|
||||
|
|
|
|||
|
|
@ -58,7 +58,7 @@
|
|||
#define I40E_PF_ARQLEN_ARQCRIT_SHIFT 30
|
||||
#define I40E_PF_ARQLEN_ARQCRIT_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQCRIT_SHIFT)
|
||||
#define I40E_PF_ARQLEN_ARQENABLE_SHIFT 31
|
||||
#define I40E_PF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQENABLE_SHIFT)
|
||||
#define I40E_PF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1u, I40E_PF_ARQLEN_ARQENABLE_SHIFT)
|
||||
#define I40E_PF_ARQT 0x00080480 /* Reset: EMPR */
|
||||
#define I40E_PF_ARQT_ARQT_SHIFT 0
|
||||
#define I40E_PF_ARQT_ARQT_MASK I40E_MASK(0x3FF, I40E_PF_ARQT_ARQT_SHIFT)
|
||||
|
|
@ -81,7 +81,7 @@
|
|||
#define I40E_PF_ATQLEN_ATQCRIT_SHIFT 30
|
||||
#define I40E_PF_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQCRIT_SHIFT)
|
||||
#define I40E_PF_ATQLEN_ATQENABLE_SHIFT 31
|
||||
#define I40E_PF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQENABLE_SHIFT)
|
||||
#define I40E_PF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1u, I40E_PF_ATQLEN_ATQENABLE_SHIFT)
|
||||
#define I40E_PF_ATQT 0x00080400 /* Reset: EMPR */
|
||||
#define I40E_PF_ATQT_ATQT_SHIFT 0
|
||||
#define I40E_PF_ATQT_ATQT_MASK I40E_MASK(0x3FF, I40E_PF_ATQT_ATQT_SHIFT)
|
||||
|
|
@ -108,7 +108,7 @@
|
|||
#define I40E_VF_ARQLEN_ARQCRIT_SHIFT 30
|
||||
#define I40E_VF_ARQLEN_ARQCRIT_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQCRIT_SHIFT)
|
||||
#define I40E_VF_ARQLEN_ARQENABLE_SHIFT 31
|
||||
#define I40E_VF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQENABLE_SHIFT)
|
||||
#define I40E_VF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1u, I40E_VF_ARQLEN_ARQENABLE_SHIFT)
|
||||
#define I40E_VF_ARQT(_VF) (0x00082C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
|
||||
#define I40E_VF_ARQT_MAX_INDEX 127
|
||||
#define I40E_VF_ARQT_ARQT_SHIFT 0
|
||||
|
|
@ -136,7 +136,7 @@
|
|||
#define I40E_VF_ATQLEN_ATQCRIT_SHIFT 30
|
||||
#define I40E_VF_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQCRIT_SHIFT)
|
||||
#define I40E_VF_ATQLEN_ATQENABLE_SHIFT 31
|
||||
#define I40E_VF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQENABLE_SHIFT)
|
||||
#define I40E_VF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1u, I40E_VF_ATQLEN_ATQENABLE_SHIFT)
|
||||
#define I40E_VF_ATQT(_VF) (0x00082800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
|
||||
#define I40E_VF_ATQT_MAX_INDEX 127
|
||||
#define I40E_VF_ATQT_ATQT_SHIFT 0
|
||||
|
|
@ -259,7 +259,7 @@
|
|||
#define I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT 30
|
||||
#define I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT)
|
||||
#define I40E_PRTDCB_RETSTCC_ETSTC_SHIFT 31
|
||||
#define I40E_PRTDCB_RETSTCC_ETSTC_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSTCC_ETSTC_SHIFT)
|
||||
#define I40E_PRTDCB_RETSTCC_ETSTC_MASK I40E_MASK(0x1u, I40E_PRTDCB_RETSTCC_ETSTC_SHIFT)
|
||||
#define I40E_PRTDCB_RPPMC 0x001223A0 /* Reset: CORER */
|
||||
#define I40E_PRTDCB_RPPMC_LANRPPM_SHIFT 0
|
||||
#define I40E_PRTDCB_RPPMC_LANRPPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_LANRPPM_SHIFT)
|
||||
|
|
@ -363,6 +363,12 @@
|
|||
#define I40E_GL_FWSTS_FWRI_MASK I40E_MASK(0x1, I40E_GL_FWSTS_FWRI_SHIFT)
|
||||
#define I40E_GL_FWSTS_FWS1B_SHIFT 16
|
||||
#define I40E_GL_FWSTS_FWS1B_MASK I40E_MASK(0xFF, I40E_GL_FWSTS_FWS1B_SHIFT)
|
||||
#define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_CORER_MASK I40E_MASK(0x30, I40E_GL_FWSTS_FWS1B_SHIFT)
|
||||
#define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_GLOBR_MASK I40E_MASK(0x31, I40E_GL_FWSTS_FWS1B_SHIFT)
|
||||
#define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_TRANSITION_MASK I40E_MASK(0x32, I40E_GL_FWSTS_FWS1B_SHIFT)
|
||||
#define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_NVM_MASK I40E_MASK(0x33, I40E_GL_FWSTS_FWS1B_SHIFT)
|
||||
#define I40E_X722_GL_FWSTS_FWS1B_REC_MOD_CORER_MASK I40E_MASK(0xB, I40E_GL_FWSTS_FWS1B_SHIFT)
|
||||
#define I40E_X722_GL_FWSTS_FWS1B_REC_MOD_GLOBR_MASK I40E_MASK(0xC, I40E_GL_FWSTS_FWS1B_SHIFT)
|
||||
#define I40E_GLGEN_CLKSTAT 0x000B8184 /* Reset: POR */
|
||||
#define I40E_GLGEN_CLKSTAT_CLKMODE_SHIFT 0
|
||||
#define I40E_GLGEN_CLKSTAT_CLKMODE_MASK I40E_MASK(0x1, I40E_GLGEN_CLKSTAT_CLKMODE_SHIFT)
|
||||
|
|
@ -503,7 +509,7 @@
|
|||
#define I40E_GLGEN_MSCA_MDICMD_SHIFT 30
|
||||
#define I40E_GLGEN_MSCA_MDICMD_MASK I40E_MASK(0x1, I40E_GLGEN_MSCA_MDICMD_SHIFT)
|
||||
#define I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT 31
|
||||
#define I40E_GLGEN_MSCA_MDIINPROGEN_MASK I40E_MASK(0x1, I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT)
|
||||
#define I40E_GLGEN_MSCA_MDIINPROGEN_MASK I40E_MASK(0x1u, I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT)
|
||||
#define I40E_GLGEN_MSRWD(_i) (0x0008819C + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */
|
||||
#define I40E_GLGEN_MSRWD_MAX_INDEX 3
|
||||
#define I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT 0
|
||||
|
|
@ -1242,14 +1248,14 @@
|
|||
#define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT 30
|
||||
#define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT)
|
||||
#define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT 31
|
||||
#define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT)
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#define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK I40E_MASK(0x1u, I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT)
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#define I40E_PFLAN_QALLOC 0x001C0400 /* Reset: CORER */
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#define I40E_PFLAN_QALLOC_FIRSTQ_SHIFT 0
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#define I40E_PFLAN_QALLOC_FIRSTQ_MASK I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_FIRSTQ_SHIFT)
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#define I40E_PFLAN_QALLOC_LASTQ_SHIFT 16
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#define I40E_PFLAN_QALLOC_LASTQ_MASK I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_LASTQ_SHIFT)
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#define I40E_PFLAN_QALLOC_VALID_SHIFT 31
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#define I40E_PFLAN_QALLOC_VALID_MASK I40E_MASK(0x1, I40E_PFLAN_QALLOC_VALID_SHIFT)
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#define I40E_PFLAN_QALLOC_VALID_MASK I40E_MASK(0x1u, I40E_PFLAN_QALLOC_VALID_SHIFT)
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#define I40E_QRX_ENA(_Q) (0x00120000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */
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#define I40E_QRX_ENA_MAX_INDEX 1535
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#define I40E_QRX_ENA_QENA_REQ_SHIFT 0
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|
|
@ -1658,7 +1664,7 @@
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#define I40E_GLNVM_SRCTL_START_SHIFT 30
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#define I40E_GLNVM_SRCTL_START_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_START_SHIFT)
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#define I40E_GLNVM_SRCTL_DONE_SHIFT 31
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#define I40E_GLNVM_SRCTL_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_DONE_SHIFT)
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#define I40E_GLNVM_SRCTL_DONE_MASK I40E_MASK(0x1u, I40E_GLNVM_SRCTL_DONE_SHIFT)
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#define I40E_GLNVM_SRDATA 0x000B6114 /* Reset: POR */
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#define I40E_GLNVM_SRDATA_WRDATA_SHIFT 0
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#define I40E_GLNVM_SRDATA_WRDATA_MASK I40E_MASK(0xFFFF, I40E_GLNVM_SRDATA_WRDATA_SHIFT)
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|
|
@ -3025,7 +3031,7 @@
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#define I40E_PF_VT_PFALLOC_LASTVF_SHIFT 8
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#define I40E_PF_VT_PFALLOC_LASTVF_MASK I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_LASTVF_SHIFT)
|
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#define I40E_PF_VT_PFALLOC_VALID_SHIFT 31
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#define I40E_PF_VT_PFALLOC_VALID_MASK I40E_MASK(0x1, I40E_PF_VT_PFALLOC_VALID_SHIFT)
|
||||
#define I40E_PF_VT_PFALLOC_VALID_MASK I40E_MASK(0x1u, I40E_PF_VT_PFALLOC_VALID_SHIFT)
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||||
#define I40E_VP_MDET_RX(_VF) (0x0012A000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
|
||||
#define I40E_VP_MDET_RX_MAX_INDEX 127
|
||||
#define I40E_VP_MDET_RX_VALID_SHIFT 0
|
||||
|
|
@ -3161,7 +3167,7 @@
|
|||
#define I40E_VF_ARQLEN1_ARQCRIT_SHIFT 30
|
||||
#define I40E_VF_ARQLEN1_ARQCRIT_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQCRIT_SHIFT)
|
||||
#define I40E_VF_ARQLEN1_ARQENABLE_SHIFT 31
|
||||
#define I40E_VF_ARQLEN1_ARQENABLE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQENABLE_SHIFT)
|
||||
#define I40E_VF_ARQLEN1_ARQENABLE_MASK I40E_MASK(0x1u, I40E_VF_ARQLEN1_ARQENABLE_SHIFT)
|
||||
#define I40E_VF_ARQT1 0x00007000 /* Reset: EMPR */
|
||||
#define I40E_VF_ARQT1_ARQT_SHIFT 0
|
||||
#define I40E_VF_ARQT1_ARQT_MASK I40E_MASK(0x3FF, I40E_VF_ARQT1_ARQT_SHIFT)
|
||||
|
|
@ -3184,7 +3190,7 @@
|
|||
#define I40E_VF_ATQLEN1_ATQCRIT_SHIFT 30
|
||||
#define I40E_VF_ATQLEN1_ATQCRIT_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQCRIT_SHIFT)
|
||||
#define I40E_VF_ATQLEN1_ATQENABLE_SHIFT 31
|
||||
#define I40E_VF_ATQLEN1_ATQENABLE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQENABLE_SHIFT)
|
||||
#define I40E_VF_ATQLEN1_ATQENABLE_MASK I40E_MASK(0x1u, I40E_VF_ATQLEN1_ATQENABLE_SHIFT)
|
||||
#define I40E_VF_ATQT1 0x00008400 /* Reset: EMPR */
|
||||
#define I40E_VF_ATQT1_ATQT_SHIFT 0
|
||||
#define I40E_VF_ATQT1_ATQT_MASK I40E_MASK(0x3FF, I40E_VF_ATQT1_ATQT_SHIFT)
|
||||
|
|
|
|||
|
|
@ -443,6 +443,7 @@ struct i40e_nvm_access {
|
|||
#define I40E_MODULE_SFF_8472_COMP 0x5E
|
||||
#define I40E_MODULE_SFF_8472_SWAP 0x5C
|
||||
#define I40E_MODULE_SFF_ADDR_MODE 0x04
|
||||
#define I40E_MODULE_SFF_DDM_IMPLEMENTED 0x40
|
||||
#define I40E_MODULE_TYPE_QSFP_PLUS 0x0D
|
||||
#define I40E_MODULE_TYPE_QSFP28 0x11
|
||||
#define I40E_MODULE_QSFP_MAX_LEN 640
|
||||
|
|
@ -623,6 +624,7 @@ struct i40e_hw {
|
|||
#define I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3)
|
||||
#define I40E_HW_FLAG_FW_LLDP_STOPPABLE BIT_ULL(4)
|
||||
#define I40E_HW_FLAG_FW_LLDP_PERSISTENT BIT_ULL(5)
|
||||
#define I40E_HW_FLAG_DROP_MODE BIT_ULL(7)
|
||||
u64 flags;
|
||||
|
||||
/* Used in set switch config AQ command */
|
||||
|
|
@ -1316,6 +1318,7 @@ struct i40e_hw_port_stats {
|
|||
#define I40E_SR_VPD_PTR 0x2F
|
||||
#define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
|
||||
#define I40E_SR_SW_CHECKSUM_WORD 0x3F
|
||||
#define I40E_SR_EMP_SR_SETTINGS_PTR 0x48
|
||||
|
||||
/* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
|
||||
#define I40E_SR_VPD_MODULE_MAX_SIZE 1024
|
||||
|
|
|
|||
|
|
@ -3967,10 +3967,15 @@ int i40e_ndo_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac)
|
|||
/* When the VF is resetting wait until it is done.
|
||||
* It can take up to 200 milliseconds,
|
||||
* but wait for up to 300 milliseconds to be safe.
|
||||
* If the VF is indeed in reset, the vsi pointer has
|
||||
* to show on the newly loaded vsi under pf->vsi[id].
|
||||
*/
|
||||
for (i = 0; i < 15; i++) {
|
||||
if (test_bit(I40E_VF_STATE_INIT, &vf->vf_states))
|
||||
if (test_bit(I40E_VF_STATE_INIT, &vf->vf_states)) {
|
||||
if (i > 0)
|
||||
vsi = pf->vsi[vf->lan_vsi_idx];
|
||||
break;
|
||||
}
|
||||
msleep(20);
|
||||
}
|
||||
if (!test_bit(I40E_VF_STATE_INIT, &vf->vf_states)) {
|
||||
|
|
|
|||
Loading…
Reference in New Issue