ARM: S5PC100: Use generic S5P GPIO Interrupt interface
S5PC100 SoC can use common S5P GPIO interrupt code. This patch removes specific S5PC100 gpio interrupts code and adds required defines and code to make use of common S5P code. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Joonyoung Shim
Kukjin Kim
parent
5fdc97b5d9
commit
7e47935bb7
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@ -11,7 +11,7 @@ obj- :=
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# Core support for S5PC100 system
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obj-$(CONFIG_CPU_S5PC100) += cpu.o init.o clock.o gpiolib.o irq-gpio.o
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obj-$(CONFIG_CPU_S5PC100) += cpu.o init.o clock.o gpiolib.o
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obj-$(CONFIG_CPU_S5PC100) += setup-i2c0.o
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obj-$(CONFIG_CPU_S5PC100) += dma.o
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@ -61,11 +61,6 @@
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* L3 8 4Bit None
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*/
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static int s5pc100_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
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{
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return S3C_IRQ_GPIO(chip->base + offset);
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}
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static int s5pc100_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset)
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{
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int base;
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@ -232,6 +227,7 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
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.base = S5PC100_GPH0(0),
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.ngpio = S5PC100_GPIO_H0_NR,
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.label = "GPH0",
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.to_irq = s5pc100_gpiolib_to_eint,
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},
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}, {
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.base = S5PC100_GPH1_BASE,
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@ -240,6 +236,7 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
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.base = S5PC100_GPH1(0),
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.ngpio = S5PC100_GPIO_H1_NR,
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.label = "GPH1",
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.to_irq = s5pc100_gpiolib_to_eint,
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},
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}, {
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.base = S5PC100_GPH2_BASE,
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@ -248,6 +245,7 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
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.base = S5PC100_GPH2(0),
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.ngpio = S5PC100_GPIO_H2_NR,
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.label = "GPH2",
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.to_irq = s5pc100_gpiolib_to_eint,
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},
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}, {
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.base = S5PC100_GPH3_BASE,
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@ -256,6 +254,7 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
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.base = S5PC100_GPH3(0),
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.ngpio = S5PC100_GPIO_H3_NR,
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.label = "GPH3",
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.to_irq = s5pc100_gpiolib_to_eint,
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},
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}, {
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.base = S5PC100_GPI_BASE,
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@ -380,47 +379,25 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
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},
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};
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/* FIXME move from irq-gpio.c */
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extern struct irq_chip s5pc100_gpioint;
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extern void s5pc100_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc);
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static __init void s5pc100_gpiolib_link(struct s3c_gpio_chip *chip)
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{
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/* Interrupt */
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if (chip->config == &gpio_cfg) {
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int i, irq;
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chip->chip.to_irq = s5pc100_gpiolib_to_irq;
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for (i = 0; i < chip->chip.ngpio; i++) {
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irq = S3C_IRQ_GPIO_BASE + chip->chip.base + i;
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set_irq_chip(irq, &s5pc100_gpioint);
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set_irq_data(irq, &chip->chip);
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set_irq_handler(irq, handle_level_irq);
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set_irq_flags(irq, IRQF_VALID);
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}
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} else if (chip->config == &gpio_cfg_eint) {
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chip->chip.to_irq = s5pc100_gpiolib_to_eint;
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}
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}
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static __init int s5pc100_gpiolib_init(void)
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{
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struct s3c_gpio_chip *chip;
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int nr_chips;
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int gpioint_group = 0;
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chip = s5pc100_gpio_chips;
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nr_chips = ARRAY_SIZE(s5pc100_gpio_chips);
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for (; nr_chips > 0; nr_chips--, chip++)
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s5pc100_gpiolib_link(chip);
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for (; nr_chips > 0; nr_chips--, chip++) {
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if (chip->config == &gpio_cfg) {
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/* gpio interrupts */
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chip->group = gpioint_group++;
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}
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}
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samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips,
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ARRAY_SIZE(s5pc100_gpio_chips));
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/* Interrupt */
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set_irq_chained_handler(IRQ_GPIOINT, s5pc100_irq_gpioint_handler);
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return 0;
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}
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core_initcall(s5pc100_gpiolib_init);
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@ -100,11 +100,12 @@
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#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0))
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#define S5P_EINT_BASE2 (IRQ_VIC_END + 1)
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#define S3C_IRQ_GPIO_BASE (IRQ_EINT(31) + 1)
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#define S3C_IRQ_GPIO(x) (S3C_IRQ_GPIO_BASE + (x))
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/* GPIO interrupt */
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#define S5P_GPIOINT_BASE (IRQ_EINT(31) + 1)
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#define S5P_GPIOINT_GROUP_MAXNR 21
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/* Until MP04 Groups -> 40 (exactly 39) Groups * 8 ~= 320 GPIOs */
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#define NR_IRQS (S3C_IRQ_GPIO(320) + 1)
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/* Set the default NR_IRQS */
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#define NR_IRQS (IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
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/* Compatibility */
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#define IRQ_LCD_FIFO IRQ_LCD0
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@ -1,266 +0,0 @@
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/*
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* arch/arm/mach-s5pc100/irq-gpio.c
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*
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* Copyright (C) 2009 Samsung Electronics
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*
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* S5PC100 - Interrupt handling for IRQ_GPIO${group}(x)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <mach/map.h>
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#include <plat/gpio-cfg.h>
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#define S5P_GPIOREG(x) (S5P_VA_GPIO + (x))
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#define CON_OFFSET 0x700
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#define MASK_OFFSET 0x900
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#define PEND_OFFSET 0xA00
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#define CON_OFFSET_2 0xE00
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#define MASK_OFFSET_2 0xF00
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#define PEND_OFFSET_2 0xF40
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#define GPIOINT_LEVEL_LOW 0x0
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#define GPIOINT_LEVEL_HIGH 0x1
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#define GPIOINT_EDGE_FALLING 0x2
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#define GPIOINT_EDGE_RISING 0x3
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#define GPIOINT_EDGE_BOTH 0x4
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static int group_to_con_offset(int group)
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{
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return group << 2;
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}
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static int group_to_mask_offset(int group)
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{
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return group << 2;
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}
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static int group_to_pend_offset(int group)
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{
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return group << 2;
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}
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static int s5pc100_get_start(unsigned int group)
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{
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switch (group) {
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case 0: return S5PC100_GPIO_A0_START;
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case 1: return S5PC100_GPIO_A1_START;
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case 2: return S5PC100_GPIO_B_START;
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case 3: return S5PC100_GPIO_C_START;
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case 4: return S5PC100_GPIO_D_START;
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case 5: return S5PC100_GPIO_E0_START;
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case 6: return S5PC100_GPIO_E1_START;
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case 7: return S5PC100_GPIO_F0_START;
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case 8: return S5PC100_GPIO_F1_START;
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case 9: return S5PC100_GPIO_F2_START;
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case 10: return S5PC100_GPIO_F3_START;
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case 11: return S5PC100_GPIO_G0_START;
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case 12: return S5PC100_GPIO_G1_START;
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case 13: return S5PC100_GPIO_G2_START;
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case 14: return S5PC100_GPIO_G3_START;
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case 15: return S5PC100_GPIO_I_START;
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case 16: return S5PC100_GPIO_J0_START;
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case 17: return S5PC100_GPIO_J1_START;
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case 18: return S5PC100_GPIO_J2_START;
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case 19: return S5PC100_GPIO_J3_START;
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case 20: return S5PC100_GPIO_J4_START;
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default:
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BUG();
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}
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return -EINVAL;
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}
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static int s5pc100_get_group(unsigned int irq)
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{
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irq -= S3C_IRQ_GPIO(0);
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switch (irq) {
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case S5PC100_GPIO_A0_START ... S5PC100_GPIO_A1_START - 1:
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return 0;
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case S5PC100_GPIO_A1_START ... S5PC100_GPIO_B_START - 1:
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return 1;
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case S5PC100_GPIO_B_START ... S5PC100_GPIO_C_START - 1:
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return 2;
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case S5PC100_GPIO_C_START ... S5PC100_GPIO_D_START - 1:
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return 3;
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case S5PC100_GPIO_D_START ... S5PC100_GPIO_E0_START - 1:
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return 4;
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case S5PC100_GPIO_E0_START ... S5PC100_GPIO_E1_START - 1:
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return 5;
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case S5PC100_GPIO_E1_START ... S5PC100_GPIO_F0_START - 1:
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return 6;
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case S5PC100_GPIO_F0_START ... S5PC100_GPIO_F1_START - 1:
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return 7;
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case S5PC100_GPIO_F1_START ... S5PC100_GPIO_F2_START - 1:
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return 8;
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case S5PC100_GPIO_F2_START ... S5PC100_GPIO_F3_START - 1:
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return 9;
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case S5PC100_GPIO_F3_START ... S5PC100_GPIO_G0_START - 1:
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return 10;
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case S5PC100_GPIO_G0_START ... S5PC100_GPIO_G1_START - 1:
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return 11;
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case S5PC100_GPIO_G1_START ... S5PC100_GPIO_G2_START - 1:
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return 12;
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case S5PC100_GPIO_G2_START ... S5PC100_GPIO_G3_START - 1:
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return 13;
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case S5PC100_GPIO_G3_START ... S5PC100_GPIO_H0_START - 1:
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return 14;
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case S5PC100_GPIO_I_START ... S5PC100_GPIO_J0_START - 1:
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return 15;
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case S5PC100_GPIO_J0_START ... S5PC100_GPIO_J1_START - 1:
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return 16;
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case S5PC100_GPIO_J1_START ... S5PC100_GPIO_J2_START - 1:
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return 17;
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case S5PC100_GPIO_J2_START ... S5PC100_GPIO_J3_START - 1:
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return 18;
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case S5PC100_GPIO_J3_START ... S5PC100_GPIO_J4_START - 1:
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return 19;
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case S5PC100_GPIO_J4_START ... S5PC100_GPIO_K0_START - 1:
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return 20;
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default:
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BUG();
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}
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return -EINVAL;
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}
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static int s5pc100_get_offset(unsigned int irq)
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{
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struct gpio_chip *chip = get_irq_data(irq);
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return irq - S3C_IRQ_GPIO(chip->base);
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}
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static void s5pc100_gpioint_ack(unsigned int irq)
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{
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int group, offset, pend_offset;
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unsigned int value;
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group = s5pc100_get_group(irq);
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offset = s5pc100_get_offset(irq);
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pend_offset = group_to_pend_offset(group);
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value = __raw_readl(S5P_GPIOREG(PEND_OFFSET) + pend_offset);
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value |= 1 << offset;
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__raw_writel(value, S5P_GPIOREG(PEND_OFFSET) + pend_offset);
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}
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static void s5pc100_gpioint_mask(unsigned int irq)
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{
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int group, offset, mask_offset;
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unsigned int value;
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group = s5pc100_get_group(irq);
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offset = s5pc100_get_offset(irq);
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mask_offset = group_to_mask_offset(group);
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value = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset);
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value |= 1 << offset;
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__raw_writel(value, S5P_GPIOREG(MASK_OFFSET) + mask_offset);
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}
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static void s5pc100_gpioint_unmask(unsigned int irq)
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{
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int group, offset, mask_offset;
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unsigned int value;
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group = s5pc100_get_group(irq);
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offset = s5pc100_get_offset(irq);
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mask_offset = group_to_mask_offset(group);
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value = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset);
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value &= ~(1 << offset);
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__raw_writel(value, S5P_GPIOREG(MASK_OFFSET) + mask_offset);
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}
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static void s5pc100_gpioint_mask_ack(unsigned int irq)
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{
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s5pc100_gpioint_mask(irq);
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s5pc100_gpioint_ack(irq);
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}
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static int s5pc100_gpioint_set_type(unsigned int irq, unsigned int type)
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{
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int group, offset, con_offset;
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unsigned int value;
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group = s5pc100_get_group(irq);
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offset = s5pc100_get_offset(irq);
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con_offset = group_to_con_offset(group);
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switch (type) {
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case IRQ_TYPE_NONE:
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printk(KERN_WARNING "No irq type\n");
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return -EINVAL;
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case IRQ_TYPE_EDGE_RISING:
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type = GPIOINT_EDGE_RISING;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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type = GPIOINT_EDGE_FALLING;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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type = GPIOINT_EDGE_BOTH;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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type = GPIOINT_LEVEL_HIGH;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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type = GPIOINT_LEVEL_LOW;
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break;
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default:
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BUG();
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}
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value = __raw_readl(S5P_GPIOREG(CON_OFFSET) + con_offset);
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value &= ~(0xf << (offset * 0x4));
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value |= (type << (offset * 0x4));
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__raw_writel(value, S5P_GPIOREG(CON_OFFSET) + con_offset);
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return 0;
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}
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struct irq_chip s5pc100_gpioint = {
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.name = "GPIO",
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.ack = s5pc100_gpioint_ack,
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.mask = s5pc100_gpioint_mask,
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.mask_ack = s5pc100_gpioint_mask_ack,
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.unmask = s5pc100_gpioint_unmask,
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.set_type = s5pc100_gpioint_set_type,
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};
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void s5pc100_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc)
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{
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int group, offset, pend_offset, mask_offset;
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int real_irq, group_end;
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unsigned int pend, mask;
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group_end = 21;
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for (group = 0; group < group_end; group++) {
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pend_offset = group_to_pend_offset(group);
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pend = __raw_readl(S5P_GPIOREG(PEND_OFFSET) + pend_offset);
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if (!pend)
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continue;
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mask_offset = group_to_mask_offset(group);
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mask = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset);
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pend &= ~mask;
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for (offset = 0; offset < 8; offset++) {
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if (pend & (1 << offset)) {
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real_irq = s5pc100_get_start(group) + offset;
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generic_handle_irq(S3C_IRQ_GPIO(real_irq));
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}
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}
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}
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}
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