Merge commit 'jwb/next' into next
This commit is contained in:
commit
7e3f36c3e1
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@ -270,7 +270,7 @@
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clock-frequency = <0>; /* Filled in by U-Boot */
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current-speed = <0>; /* Filled in by U-Boot */
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interrupt-parent = <&UIC1>;
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interrupts = <0x1d 0x4>;
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interrupts = <28 0x4>;
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};
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UART3: serial@ef600600 {
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@ -281,7 +281,7 @@
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clock-frequency = <0>; /* Filled in by U-Boot */
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current-speed = <0>; /* Filled in by U-Boot */
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interrupt-parent = <&UIC1>;
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interrupts = <0x1e 0x4>;
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interrupts = <29 0x4>;
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};
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IIC0: i2c@ef600700 {
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@ -259,7 +259,7 @@
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clock-frequency = <0>; /* Filled in by U-Boot */
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current-speed = <0>; /* Filled in by U-Boot */
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interrupt-parent = <&UIC1>;
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interrupts = <0x1d 0x4>;
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interrupts = <28 0x4>;
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};
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UART3: serial@ef600600 {
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@ -270,7 +270,7 @@
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clock-frequency = <0>; /* Filled in by U-Boot */
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current-speed = <0>; /* Filled in by U-Boot */
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interrupt-parent = <&UIC1>;
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interrupts = <0x1e 0x4>;
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interrupts = <29 0x4>;
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};
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IIC0: i2c@ef600700 {
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@ -1364,10 +1364,10 @@ static struct cpu_spec __initdata cpu_specs[] = {
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.machine_check = machine_check_4xx,
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.platform = "ppc405",
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},
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{ /* 405EX */
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.pvr_mask = 0xffff0004,
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.pvr_value = 0x12910004,
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.cpu_name = "405EX",
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{ /* 405EX Rev. A/B with Security */
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.pvr_mask = 0xffff000f,
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.pvr_value = 0x12910007,
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.cpu_name = "405EX Rev. A/B",
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.cpu_features = CPU_FTRS_40X,
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.cpu_user_features = PPC_FEATURE_32 |
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PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
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@ -1377,10 +1377,114 @@ static struct cpu_spec __initdata cpu_specs[] = {
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.machine_check = machine_check_4xx,
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.platform = "ppc405",
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},
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{ /* 405EXr */
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.pvr_mask = 0xffff0004,
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{ /* 405EX Rev. C without Security */
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.pvr_mask = 0xffff000f,
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.pvr_value = 0x1291000d,
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.cpu_name = "405EX Rev. C",
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.cpu_features = CPU_FTRS_40X,
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.cpu_user_features = PPC_FEATURE_32 |
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PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
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.mmu_features = MMU_FTR_TYPE_40x,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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.machine_check = machine_check_4xx,
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.platform = "ppc405",
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},
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{ /* 405EX Rev. C with Security */
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.pvr_mask = 0xffff000f,
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.pvr_value = 0x1291000f,
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.cpu_name = "405EX Rev. C",
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.cpu_features = CPU_FTRS_40X,
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.cpu_user_features = PPC_FEATURE_32 |
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PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
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.mmu_features = MMU_FTR_TYPE_40x,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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.machine_check = machine_check_4xx,
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.platform = "ppc405",
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},
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{ /* 405EX Rev. D without Security */
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.pvr_mask = 0xffff000f,
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.pvr_value = 0x12910003,
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.cpu_name = "405EX Rev. D",
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.cpu_features = CPU_FTRS_40X,
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.cpu_user_features = PPC_FEATURE_32 |
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PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
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.mmu_features = MMU_FTR_TYPE_40x,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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.machine_check = machine_check_4xx,
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.platform = "ppc405",
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},
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{ /* 405EX Rev. D with Security */
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.pvr_mask = 0xffff000f,
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.pvr_value = 0x12910005,
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.cpu_name = "405EX Rev. D",
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.cpu_features = CPU_FTRS_40X,
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.cpu_user_features = PPC_FEATURE_32 |
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PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
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.mmu_features = MMU_FTR_TYPE_40x,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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.machine_check = machine_check_4xx,
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.platform = "ppc405",
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},
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{ /* 405EXr Rev. A/B without Security */
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.pvr_mask = 0xffff000f,
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.pvr_value = 0x12910001,
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.cpu_name = "405EXr Rev. A/B",
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.cpu_features = CPU_FTRS_40X,
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.cpu_user_features = PPC_FEATURE_32 |
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PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
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.mmu_features = MMU_FTR_TYPE_40x,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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.machine_check = machine_check_4xx,
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.platform = "ppc405",
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},
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{ /* 405EXr Rev. C without Security */
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.pvr_mask = 0xffff000f,
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.pvr_value = 0x12910009,
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.cpu_name = "405EXr Rev. C",
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.cpu_features = CPU_FTRS_40X,
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.cpu_user_features = PPC_FEATURE_32 |
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PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
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.mmu_features = MMU_FTR_TYPE_40x,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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.machine_check = machine_check_4xx,
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.platform = "ppc405",
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},
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{ /* 405EXr Rev. C with Security */
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.pvr_mask = 0xffff000f,
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.pvr_value = 0x1291000b,
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.cpu_name = "405EXr Rev. C",
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.cpu_features = CPU_FTRS_40X,
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.cpu_user_features = PPC_FEATURE_32 |
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PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
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.mmu_features = MMU_FTR_TYPE_40x,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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.machine_check = machine_check_4xx,
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.platform = "ppc405",
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},
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{ /* 405EXr Rev. D without Security */
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.pvr_mask = 0xffff000f,
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.pvr_value = 0x12910000,
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.cpu_name = "405EXr",
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.cpu_name = "405EXr Rev. D",
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.cpu_features = CPU_FTRS_40X,
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.cpu_user_features = PPC_FEATURE_32 |
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PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
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.mmu_features = MMU_FTR_TYPE_40x,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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.machine_check = machine_check_4xx,
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.platform = "ppc405",
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},
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{ /* 405EXr Rev. D with Security */
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.pvr_mask = 0xffff000f,
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.pvr_value = 0x12910002,
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.cpu_name = "405EXr Rev. D",
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.cpu_features = CPU_FTRS_40X,
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.cpu_user_features = PPC_FEATURE_32 |
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PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
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@ -71,22 +71,6 @@ config MAKALU
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help
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This option enables support for the AMCC PPC405EX board.
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#config REDWOOD_5
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# bool "Redwood-5"
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# depends on 40x
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# default n
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# select STB03xxx
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# help
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# This option enables support for the IBM STB04 evaluation board.
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#config REDWOOD_6
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# bool "Redwood-6"
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# depends on 40x
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# default n
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# select STB03xxx
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# help
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# This option enables support for the IBM STBx25xx evaluation board.
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#config SYCAMORE
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# bool "Sycamore"
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# depends on 40x
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@ -321,7 +321,7 @@ config MTD_CFI_FLAGADM
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config MTD_REDWOOD
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tristate "CFI Flash devices mapped on IBM Redwood"
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depends on MTD_CFI && ( REDWOOD_4 || REDWOOD_5 || REDWOOD_6 )
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depends on MTD_CFI
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help
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This enables access routines for the flash chips on the IBM
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Redwood board. If you have one of these boards and would like to
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@ -22,8 +22,6 @@
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#include <asm/io.h>
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#if !defined (CONFIG_REDWOOD_6)
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#define WINDOW_ADDR 0xffc00000
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#define WINDOW_SIZE 0x00400000
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@ -69,47 +67,6 @@ static struct mtd_partition redwood_flash_partitions[] = {
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}
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};
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#else /* CONFIG_REDWOOD_6 */
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/* FIXME: the window is bigger - armin */
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#define WINDOW_ADDR 0xff800000
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#define WINDOW_SIZE 0x00800000
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#define RW_PART0_OF 0
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#define RW_PART0_SZ 0x400000 /* 4 MiB data */
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#define RW_PART1_OF RW_PART0_OF + RW_PART0_SZ
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#define RW_PART1_SZ 0x10000 /* 64K VPD */
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#define RW_PART2_OF RW_PART1_OF + RW_PART1_SZ
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#define RW_PART2_SZ 0x400000 - (0x10000 + 0x20000)
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#define RW_PART3_OF RW_PART2_OF + RW_PART2_SZ
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#define RW_PART3_SZ 0x20000
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static struct mtd_partition redwood_flash_partitions[] = {
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{
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.name = "Redwood filesystem",
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.offset = RW_PART0_OF,
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.size = RW_PART0_SZ
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},
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{
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.name = "Redwood OpenBIOS Vital Product Data",
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.offset = RW_PART1_OF,
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.size = RW_PART1_SZ,
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.mask_flags = MTD_WRITEABLE /* force read-only */
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},
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{
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.name = "Redwood kernel",
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.offset = RW_PART2_OF,
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.size = RW_PART2_SZ
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},
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{
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.name = "Redwood OpenBIOS",
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.offset = RW_PART3_OF,
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.size = RW_PART3_SZ,
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.mask_flags = MTD_WRITEABLE /* force read-only */
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}
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};
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#endif /* CONFIG_REDWOOD_6 */
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struct map_info redwood_flash_map = {
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.name = "IBM Redwood",
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.size = WINDOW_SIZE,
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@ -913,7 +913,7 @@ config SMC91X
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tristate "SMC 91C9x/91C1xxx support"
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select CRC32
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select MII
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depends on ARM || REDWOOD_5 || REDWOOD_6 || M32R || SUPERH || \
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depends on ARM || M32R || SUPERH || \
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MIPS || BLACKFIN || MN10300 || COLDFIRE
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help
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This is a driver for SMC's 91x series of Ethernet chipsets,
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@ -83,43 +83,6 @@ static inline void SMC_outw(u16 val, void __iomem *ioaddr, int reg)
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}
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}
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#elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)
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/* We can only do 16-bit reads and writes in the static memory space. */
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#define SMC_CAN_USE_8BIT 0
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#define SMC_CAN_USE_16BIT 1
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#define SMC_CAN_USE_32BIT 0
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#define SMC_NOWAIT 1
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#define SMC_IO_SHIFT 0
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#define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r)))
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#define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v)
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#define SMC_insw(a, r, p, l) \
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do { \
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unsigned long __port = (a) + (r); \
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u16 *__p = (u16 *)(p); \
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int __l = (l); \
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insw(__port, __p, __l); \
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while (__l > 0) { \
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*__p = swab16(*__p); \
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__p++; \
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__l--; \
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} \
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} while (0)
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#define SMC_outsw(a, r, p, l) \
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do { \
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unsigned long __port = (a) + (r); \
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u16 *__p = (u16 *)(p); \
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int __l = (l); \
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while (__l > 0) { \
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/* Believe it or not, the swab isn't needed. */ \
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outw( /* swab16 */ (*__p++), __port); \
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__l--; \
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} \
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} while (0)
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#define SMC_IRQ_FLAGS (0)
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#elif defined(CONFIG_SA1100_PLEB)
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/* We can only do 16-bit reads and writes in the static memory space. */
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#define SMC_CAN_USE_8BIT 1
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