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drm/amd/display: allow windowed mpo + odm 

This change adds a config flag to allow non fullscreen MPO during ODM.
Scaling calculation will still fail configurations where video is only
one one side of the screen.

Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Acked-by: Agustin Gutierrez <agustin.gutierrez@amd.com>
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dmytro Laktyushkin 2021-07-19 11:07:30 -04:00 committed by Alex Deucher
parent b8f0208858
commit 7db581d661
3 changed files with 28 additions and 17 deletions
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14
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
View File

@ -1155,9 +1155,17 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
pipe_ctx->plane_res.scl_data.recout.x += pipe_ctx->plane_res.scl_data.recout.width;
}
if (pipe_ctx->plane_res.scl_data.viewport.height < MIN_VIEWPORT_SIZE ||
pipe_ctx->plane_res.scl_data.viewport.width < MIN_VIEWPORT_SIZE)
res = false;
if (!pipe_ctx->stream->ctx->dc->config.enable_windowed_mpo_odm) {
if (pipe_ctx->plane_res.scl_data.viewport.height < MIN_VIEWPORT_SIZE ||
pipe_ctx->plane_res.scl_data.viewport.width < MIN_VIEWPORT_SIZE)
res = false;
} else {
/* Clamp minimum viewport size */
if (pipe_ctx->plane_res.scl_data.viewport.height < MIN_VIEWPORT_SIZE)
pipe_ctx->plane_res.scl_data.viewport.height = MIN_VIEWPORT_SIZE;
if (pipe_ctx->plane_res.scl_data.viewport.width < MIN_VIEWPORT_SIZE)
pipe_ctx->plane_res.scl_data.viewport.width = MIN_VIEWPORT_SIZE;
}
DC_LOG_SCALER("%s pipe %d:\nViewport: height:%d width:%d x:%d y:%d Recout: height:%d width:%d x:%d y:%d HACTIVE:%d VACTIVE:%d\n"
"src_rect: height:%d width:%d x:%d y:%d dst_rect: height:%d width:%d x:%d y:%d clip_rect: height:%d width:%d x:%d y:%d\n",

1
drivers/gpu/drm/amd/display/dc/dc.h
View File

@ -323,6 +323,7 @@ struct dc_config {
bool multi_mon_pp_mclk_switch;
bool disable_dmcu;
bool enable_4to1MPC;
bool enable_windowed_mpo_odm;
bool allow_edp_hotplug_detection;
#if defined(CONFIG_DRM_AMD_DC_DCN)
bool clamp_min_dcfclk;

30
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
View File

@ -1929,23 +1929,25 @@ noinline bool dcn30_internal_validate_bw(
if (vlevel == context->bw_ctx.dml.soc.num_states)
goto validate_fail;
for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
if (!dc->config.enable_windowed_mpo_odm) {
for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
if (!pipe->stream)
continue;
if (!pipe->stream)
continue;
/* We only support full screen mpo with ODM */
if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
&& pipe->plane_state && mpo_pipe
&& memcmp(&mpo_pipe->plane_res.scl_data.recout,
&pipe->plane_res.scl_data.recout,
sizeof(struct rect)) != 0) {
ASSERT(mpo_pipe->plane_state != pipe->plane_state);
goto validate_fail;
/* We only support full screen mpo with ODM */
if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
&& pipe->plane_state && mpo_pipe
&& memcmp(&mpo_pipe->plane_res.scl_data.recout,
&pipe->plane_res.scl_data.recout,
sizeof(struct rect)) != 0) {
ASSERT(mpo_pipe->plane_state != pipe->plane_state);
goto validate_fail;
}
pipe_idx++;
}
pipe_idx++;
}
/* merge pipes if necessary */