drm/i915: Tweak plane ddb allocation tracking
Let's store the plane allocation in a manner which more closely matches how the hw operates. That is, we store the packed/CbCr ddb in one struct, and the Y ddb in another. Currently we're storing packed/Y in one struct, CbCr in the other. This also works pretty well for icl+ where the UV plane is the main plane and the Y plane is subservient to it. Although in this case we do not even use ddb_y as we do the ddb allocation in terms of hw planes. v2: Rebase Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220303191207.27931-2-ville.syrjala@linux.intel.com
This commit is contained in:
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7d4561722c
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@ -616,8 +616,8 @@ int intel_plane_atomic_check(struct intel_atomic_state *state,
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static struct intel_plane *
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static struct intel_plane *
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skl_next_plane_to_commit(struct intel_atomic_state *state,
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skl_next_plane_to_commit(struct intel_atomic_state *state,
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struct intel_crtc *crtc,
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struct intel_crtc *crtc,
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struct skl_ddb_entry entries_y[I915_MAX_PLANES],
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struct skl_ddb_entry ddb[I915_MAX_PLANES],
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struct skl_ddb_entry entries_uv[I915_MAX_PLANES],
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struct skl_ddb_entry ddb_y[I915_MAX_PLANES],
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unsigned int *update_mask)
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unsigned int *update_mask)
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{
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{
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struct intel_crtc_state *crtc_state =
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struct intel_crtc_state *crtc_state =
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@ -636,17 +636,15 @@ skl_next_plane_to_commit(struct intel_atomic_state *state,
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!(*update_mask & BIT(plane_id)))
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!(*update_mask & BIT(plane_id)))
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continue;
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continue;
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if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id],
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if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb[plane_id],
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entries_y,
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ddb, I915_MAX_PLANES, plane_id) ||
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I915_MAX_PLANES, plane_id) ||
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skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id],
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skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_uv[plane_id],
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ddb_y, I915_MAX_PLANES, plane_id))
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entries_uv,
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I915_MAX_PLANES, plane_id))
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continue;
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continue;
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*update_mask &= ~BIT(plane_id);
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*update_mask &= ~BIT(plane_id);
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entries_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id];
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ddb[plane_id] = crtc_state->wm.skl.plane_ddb[plane_id];
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entries_uv[plane_id] = crtc_state->wm.skl.plane_ddb_uv[plane_id];
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ddb_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id];
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return plane;
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return plane;
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}
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}
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@ -728,19 +726,17 @@ static void skl_crtc_planes_update_arm(struct intel_atomic_state *state,
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intel_atomic_get_old_crtc_state(state, crtc);
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intel_atomic_get_old_crtc_state(state, crtc);
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struct intel_crtc_state *new_crtc_state =
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struct intel_crtc_state *new_crtc_state =
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intel_atomic_get_new_crtc_state(state, crtc);
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intel_atomic_get_new_crtc_state(state, crtc);
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struct skl_ddb_entry entries_y[I915_MAX_PLANES];
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struct skl_ddb_entry ddb[I915_MAX_PLANES];
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struct skl_ddb_entry entries_uv[I915_MAX_PLANES];
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struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
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u32 update_mask = new_crtc_state->update_planes;
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u32 update_mask = new_crtc_state->update_planes;
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struct intel_plane *plane;
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struct intel_plane *plane;
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memcpy(entries_y, old_crtc_state->wm.skl.plane_ddb_y,
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memcpy(ddb, old_crtc_state->wm.skl.plane_ddb,
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sizeof(old_crtc_state->wm.skl.plane_ddb));
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memcpy(ddb_y, old_crtc_state->wm.skl.plane_ddb_y,
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sizeof(old_crtc_state->wm.skl.plane_ddb_y));
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sizeof(old_crtc_state->wm.skl.plane_ddb_y));
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memcpy(entries_uv, old_crtc_state->wm.skl.plane_ddb_uv,
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sizeof(old_crtc_state->wm.skl.plane_ddb_uv));
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while ((plane = skl_next_plane_to_commit(state, crtc,
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while ((plane = skl_next_plane_to_commit(state, crtc, ddb, ddb_y, &update_mask))) {
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entries_y, entries_uv,
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&update_mask))) {
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struct intel_plane_state *new_plane_state =
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struct intel_plane_state *new_plane_state =
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intel_atomic_get_new_plane_state(state, plane);
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intel_atomic_get_new_plane_state(state, plane);
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@ -688,16 +688,16 @@ static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state,
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return;
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return;
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for_each_plane_id_on_crtc(crtc, plane_id) {
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for_each_plane_id_on_crtc(crtc, plane_id) {
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const struct skl_ddb_entry *ddb =
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&crtc_state->wm.skl.plane_ddb[plane_id];
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const struct skl_ddb_entry *ddb_y =
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const struct skl_ddb_entry *ddb_y =
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&crtc_state->wm.skl.plane_ddb_y[plane_id];
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&crtc_state->wm.skl.plane_ddb_y[plane_id];
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const struct skl_ddb_entry *ddb_uv =
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&crtc_state->wm.skl.plane_ddb_uv[plane_id];
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unsigned int data_rate = crtc_state->data_rate[plane_id];
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unsigned int data_rate = crtc_state->data_rate[plane_id];
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unsigned int dbuf_mask = 0;
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unsigned int dbuf_mask = 0;
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enum dbuf_slice slice;
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enum dbuf_slice slice;
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dbuf_mask |= skl_ddb_dbuf_slice_mask(i915, ddb);
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dbuf_mask |= skl_ddb_dbuf_slice_mask(i915, ddb_y);
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dbuf_mask |= skl_ddb_dbuf_slice_mask(i915, ddb_y);
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dbuf_mask |= skl_ddb_dbuf_slice_mask(i915, ddb_uv);
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/*
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/*
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* FIXME: To calculate that more properly we probably
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* FIXME: To calculate that more properly we probably
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@ -6508,8 +6508,8 @@ static void verify_wm_state(struct intel_crtc *crtc,
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{
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{
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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struct skl_hw_state {
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struct skl_hw_state {
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struct skl_ddb_entry ddb[I915_MAX_PLANES];
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struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
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struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
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struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
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struct skl_pipe_wm wm;
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struct skl_pipe_wm wm;
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} *hw;
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} *hw;
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const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal;
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const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal;
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@ -6526,7 +6526,7 @@ static void verify_wm_state(struct intel_crtc *crtc,
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skl_pipe_wm_get_hw_state(crtc, &hw->wm);
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skl_pipe_wm_get_hw_state(crtc, &hw->wm);
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skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
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skl_pipe_ddb_get_hw_state(crtc, hw->ddb, hw->ddb_y);
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hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv);
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hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv);
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@ -6608,8 +6608,8 @@ static void verify_wm_state(struct intel_crtc *crtc,
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}
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}
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/* DDB */
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/* DDB */
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hw_ddb_entry = &hw->ddb_y[plane->id];
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hw_ddb_entry = &hw->ddb[PLANE_CURSOR];
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sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane->id];
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sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb[PLANE_CURSOR];
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if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
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if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
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drm_err(&dev_priv->drm,
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drm_err(&dev_priv->drm,
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@ -1125,13 +1125,13 @@ static int i915_ddb_info(struct seq_file *m, void *unused)
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seq_printf(m, "Pipe %c\n", pipe_name(pipe));
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seq_printf(m, "Pipe %c\n", pipe_name(pipe));
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for_each_plane_id_on_crtc(crtc, plane_id) {
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for_each_plane_id_on_crtc(crtc, plane_id) {
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entry = &crtc_state->wm.skl.plane_ddb_y[plane_id];
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entry = &crtc_state->wm.skl.plane_ddb[plane_id];
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seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane_id + 1,
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seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane_id + 1,
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entry->start, entry->end,
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entry->start, entry->end,
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skl_ddb_entry_size(entry));
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skl_ddb_entry_size(entry));
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}
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}
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entry = &crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR];
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entry = &crtc_state->wm.skl.plane_ddb[PLANE_CURSOR];
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seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
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seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
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entry->end, skl_ddb_entry_size(entry));
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entry->end, skl_ddb_entry_size(entry));
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}
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}
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@ -846,8 +846,13 @@ struct intel_crtc_wm_state {
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/* gen9+ only needs 1-step wm programming */
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/* gen9+ only needs 1-step wm programming */
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struct skl_pipe_wm optimal;
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struct skl_pipe_wm optimal;
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struct skl_ddb_entry ddb;
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struct skl_ddb_entry ddb;
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/*
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* pre-icl: for packed/planar CbCr
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* icl+: for everything
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*/
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struct skl_ddb_entry plane_ddb[I915_MAX_PLANES];
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/* pre-icl: for planar Y */
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struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
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struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
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struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES];
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} skl;
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} skl;
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struct {
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struct {
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@ -4346,46 +4346,31 @@ static void
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skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
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skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
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const enum pipe pipe,
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const enum pipe pipe,
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const enum plane_id plane_id,
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const enum plane_id plane_id,
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struct skl_ddb_entry *ddb_y,
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struct skl_ddb_entry *ddb,
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struct skl_ddb_entry *ddb_uv)
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struct skl_ddb_entry *ddb_y)
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{
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{
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u32 val, val2;
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u32 val;
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u32 fourcc = 0;
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/* Cursor doesn't support NV12/planar, so no extra calculation needed */
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/* Cursor doesn't support NV12/planar, so no extra calculation needed */
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if (plane_id == PLANE_CURSOR) {
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if (plane_id == PLANE_CURSOR) {
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val = intel_uncore_read(&dev_priv->uncore, CUR_BUF_CFG(pipe));
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val = intel_uncore_read(&dev_priv->uncore, CUR_BUF_CFG(pipe));
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skl_ddb_entry_init_from_hw(ddb_y, val);
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skl_ddb_entry_init_from_hw(ddb, val);
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return;
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return;
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}
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}
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val = intel_uncore_read(&dev_priv->uncore, PLANE_CTL(pipe, plane_id));
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val = intel_uncore_read(&dev_priv->uncore, PLANE_BUF_CFG(pipe, plane_id));
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skl_ddb_entry_init_from_hw(ddb, val);
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/* No DDB allocated for disabled planes */
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if (DISPLAY_VER(dev_priv) >= 11)
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if (val & PLANE_CTL_ENABLE)
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return;
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fourcc = skl_format_to_fourcc(val & PLANE_CTL_FORMAT_MASK_SKL,
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val & PLANE_CTL_ORDER_RGBX,
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val & PLANE_CTL_ALPHA_MASK);
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if (DISPLAY_VER(dev_priv) >= 11) {
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val = intel_uncore_read(&dev_priv->uncore, PLANE_NV12_BUF_CFG(pipe, plane_id));
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val = intel_uncore_read(&dev_priv->uncore, PLANE_BUF_CFG(pipe, plane_id));
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skl_ddb_entry_init_from_hw(ddb_y, val);
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skl_ddb_entry_init_from_hw(ddb_y, val);
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} else {
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val = intel_uncore_read(&dev_priv->uncore, PLANE_BUF_CFG(pipe, plane_id));
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val2 = intel_uncore_read(&dev_priv->uncore, PLANE_NV12_BUF_CFG(pipe, plane_id));
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if (fourcc &&
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drm_format_info_is_yuv_semiplanar(drm_format_info(fourcc)))
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swap(val, val2);
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skl_ddb_entry_init_from_hw(ddb_y, val);
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skl_ddb_entry_init_from_hw(ddb_uv, val2);
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}
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}
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}
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void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
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void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
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struct skl_ddb_entry *ddb_y,
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struct skl_ddb_entry *ddb,
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struct skl_ddb_entry *ddb_uv)
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struct skl_ddb_entry *ddb_y)
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{
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{
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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enum intel_display_power_domain power_domain;
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enum intel_display_power_domain power_domain;
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@ -4401,8 +4386,8 @@ void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
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for_each_plane_id_on_crtc(crtc, plane_id)
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for_each_plane_id_on_crtc(crtc, plane_id)
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skl_ddb_get_hw_plane_state(dev_priv, pipe,
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skl_ddb_get_hw_plane_state(dev_priv, pipe,
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plane_id,
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plane_id,
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&ddb_y[plane_id],
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&ddb[plane_id],
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&ddb_uv[plane_id]);
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&ddb_y[plane_id]);
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intel_display_power_put(dev_priv, power_domain, wakeref);
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intel_display_power_put(dev_priv, power_domain, wakeref);
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}
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}
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@ -5195,8 +5180,8 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
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int level;
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int level;
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/* Clear the partitioning for disabled planes. */
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/* Clear the partitioning for disabled planes. */
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memset(crtc_state->wm.skl.plane_ddb, 0, sizeof(crtc_state->wm.skl.plane_ddb));
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memset(crtc_state->wm.skl.plane_ddb_y, 0, sizeof(crtc_state->wm.skl.plane_ddb_y));
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memset(crtc_state->wm.skl.plane_ddb_y, 0, sizeof(crtc_state->wm.skl.plane_ddb_y));
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memset(crtc_state->wm.skl.plane_ddb_uv, 0, sizeof(crtc_state->wm.skl.plane_ddb_uv));
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if (!crtc_state->hw.active)
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if (!crtc_state->hw.active)
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return 0;
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return 0;
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@ -5213,7 +5198,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
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/* Allocate fixed number of blocks for cursor. */
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/* Allocate fixed number of blocks for cursor. */
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iter.total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, num_active);
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iter.total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, num_active);
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iter.size -= iter.total[PLANE_CURSOR];
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iter.size -= iter.total[PLANE_CURSOR];
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skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR],
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skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[PLANE_CURSOR],
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alloc->end - iter.total[PLANE_CURSOR], alloc->end);
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alloc->end - iter.total[PLANE_CURSOR], alloc->end);
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/*
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/*
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@ -5283,10 +5268,10 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
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/* Set the actual DDB start/end points for each plane */
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/* Set the actual DDB start/end points for each plane */
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iter.start = alloc->start;
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iter.start = alloc->start;
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for_each_plane_id_on_crtc(crtc, plane_id) {
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for_each_plane_id_on_crtc(crtc, plane_id) {
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struct skl_ddb_entry *plane_alloc =
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struct skl_ddb_entry *ddb =
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&crtc_state->wm.skl.plane_ddb[plane_id];
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struct skl_ddb_entry *ddb_y =
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&crtc_state->wm.skl.plane_ddb_y[plane_id];
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&crtc_state->wm.skl.plane_ddb_y[plane_id];
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struct skl_ddb_entry *uv_plane_alloc =
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&crtc_state->wm.skl.plane_ddb_uv[plane_id];
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if (plane_id == PLANE_CURSOR)
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if (plane_id == PLANE_CURSOR)
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continue;
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continue;
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@ -5297,12 +5282,15 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
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/* Leave disabled planes at (0,0) */
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/* Leave disabled planes at (0,0) */
|
||||||
if (iter.total[plane_id])
|
if (iter.total[plane_id])
|
||||||
iter.start = skl_ddb_entry_init(plane_alloc, iter.start,
|
iter.start = skl_ddb_entry_init(ddb, iter.start,
|
||||||
iter.start + iter.total[plane_id]);
|
iter.start + iter.total[plane_id]);
|
||||||
|
|
||||||
if (iter.uv_total[plane_id])
|
if (iter.uv_total[plane_id]) {
|
||||||
iter.start = skl_ddb_entry_init(uv_plane_alloc, iter.start,
|
/* hardware wants these swapped */
|
||||||
|
*ddb_y = *ddb;
|
||||||
|
iter.start = skl_ddb_entry_init(ddb, iter.start,
|
||||||
iter.start + iter.uv_total[plane_id]);
|
iter.start + iter.uv_total[plane_id]);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -5962,11 +5950,10 @@ void skl_write_plane_wm(struct intel_plane *plane,
|
||||||
enum plane_id plane_id = plane->id;
|
enum plane_id plane_id = plane->id;
|
||||||
enum pipe pipe = plane->pipe;
|
enum pipe pipe = plane->pipe;
|
||||||
const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
|
const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
|
||||||
const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
|
const struct skl_ddb_entry *ddb =
|
||||||
|
&crtc_state->wm.skl.plane_ddb[plane_id];
|
||||||
const struct skl_ddb_entry *ddb_y =
|
const struct skl_ddb_entry *ddb_y =
|
||||||
&crtc_state->wm.skl.plane_ddb_y[plane_id];
|
&crtc_state->wm.skl.plane_ddb_y[plane_id];
|
||||||
const struct skl_ddb_entry *ddb_uv =
|
|
||||||
&crtc_state->wm.skl.plane_ddb_uv[plane_id];
|
|
||||||
|
|
||||||
for (level = 0; level <= max_level; level++)
|
for (level = 0; level <= max_level; level++)
|
||||||
skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
|
skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
|
||||||
|
@ -5976,25 +5963,20 @@ void skl_write_plane_wm(struct intel_plane *plane,
|
||||||
skl_plane_trans_wm(pipe_wm, plane_id));
|
skl_plane_trans_wm(pipe_wm, plane_id));
|
||||||
|
|
||||||
if (HAS_HW_SAGV_WM(dev_priv)) {
|
if (HAS_HW_SAGV_WM(dev_priv)) {
|
||||||
|
const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
|
||||||
|
|
||||||
skl_write_wm_level(dev_priv, PLANE_WM_SAGV(pipe, plane_id),
|
skl_write_wm_level(dev_priv, PLANE_WM_SAGV(pipe, plane_id),
|
||||||
&wm->sagv.wm0);
|
&wm->sagv.wm0);
|
||||||
skl_write_wm_level(dev_priv, PLANE_WM_SAGV_TRANS(pipe, plane_id),
|
skl_write_wm_level(dev_priv, PLANE_WM_SAGV_TRANS(pipe, plane_id),
|
||||||
&wm->sagv.trans_wm);
|
&wm->sagv.trans_wm);
|
||||||
}
|
}
|
||||||
|
|
||||||
if (DISPLAY_VER(dev_priv) >= 11) {
|
skl_ddb_entry_write(dev_priv,
|
||||||
|
PLANE_BUF_CFG(pipe, plane_id), ddb);
|
||||||
|
|
||||||
|
if (DISPLAY_VER(dev_priv) < 11)
|
||||||
skl_ddb_entry_write(dev_priv,
|
skl_ddb_entry_write(dev_priv,
|
||||||
PLANE_BUF_CFG(pipe, plane_id), ddb_y);
|
PLANE_NV12_BUF_CFG(pipe, plane_id), ddb_y);
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (wm->is_planar)
|
|
||||||
swap(ddb_y, ddb_uv);
|
|
||||||
|
|
||||||
skl_ddb_entry_write(dev_priv,
|
|
||||||
PLANE_BUF_CFG(pipe, plane_id), ddb_y);
|
|
||||||
skl_ddb_entry_write(dev_priv,
|
|
||||||
PLANE_NV12_BUF_CFG(pipe, plane_id), ddb_uv);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void skl_write_cursor_wm(struct intel_plane *plane,
|
void skl_write_cursor_wm(struct intel_plane *plane,
|
||||||
|
@ -6006,7 +5988,7 @@ void skl_write_cursor_wm(struct intel_plane *plane,
|
||||||
enum pipe pipe = plane->pipe;
|
enum pipe pipe = plane->pipe;
|
||||||
const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
|
const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
|
||||||
const struct skl_ddb_entry *ddb =
|
const struct skl_ddb_entry *ddb =
|
||||||
&crtc_state->wm.skl.plane_ddb_y[plane_id];
|
&crtc_state->wm.skl.plane_ddb[plane_id];
|
||||||
|
|
||||||
for (level = 0; level <= max_level; level++)
|
for (level = 0; level <= max_level; level++)
|
||||||
skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
|
skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
|
||||||
|
@ -6103,10 +6085,10 @@ skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state,
|
||||||
struct intel_plane_state *plane_state;
|
struct intel_plane_state *plane_state;
|
||||||
enum plane_id plane_id = plane->id;
|
enum plane_id plane_id = plane->id;
|
||||||
|
|
||||||
if (skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_y[plane_id],
|
if (skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb[plane_id],
|
||||||
&new_crtc_state->wm.skl.plane_ddb_y[plane_id]) &&
|
&new_crtc_state->wm.skl.plane_ddb[plane_id]) &&
|
||||||
skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_uv[plane_id],
|
skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_y[plane_id],
|
||||||
&new_crtc_state->wm.skl.plane_ddb_uv[plane_id]))
|
&new_crtc_state->wm.skl.plane_ddb_y[plane_id]))
|
||||||
continue;
|
continue;
|
||||||
|
|
||||||
plane_state = intel_atomic_get_plane_state(state, plane);
|
plane_state = intel_atomic_get_plane_state(state, plane);
|
||||||
|
@ -6275,8 +6257,8 @@ skl_print_wm_changes(struct intel_atomic_state *state)
|
||||||
enum plane_id plane_id = plane->id;
|
enum plane_id plane_id = plane->id;
|
||||||
const struct skl_ddb_entry *old, *new;
|
const struct skl_ddb_entry *old, *new;
|
||||||
|
|
||||||
old = &old_crtc_state->wm.skl.plane_ddb_y[plane_id];
|
old = &old_crtc_state->wm.skl.plane_ddb[plane_id];
|
||||||
new = &new_crtc_state->wm.skl.plane_ddb_y[plane_id];
|
new = &new_crtc_state->wm.skl.plane_ddb[plane_id];
|
||||||
|
|
||||||
if (skl_ddb_entry_equal(old, new))
|
if (skl_ddb_entry_equal(old, new))
|
||||||
continue;
|
continue;
|
||||||
|
@ -6678,16 +6660,16 @@ void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
|
||||||
memset(&dbuf_state->ddb[pipe], 0, sizeof(dbuf_state->ddb[pipe]));
|
memset(&dbuf_state->ddb[pipe], 0, sizeof(dbuf_state->ddb[pipe]));
|
||||||
|
|
||||||
for_each_plane_id_on_crtc(crtc, plane_id) {
|
for_each_plane_id_on_crtc(crtc, plane_id) {
|
||||||
|
struct skl_ddb_entry *ddb =
|
||||||
|
&crtc_state->wm.skl.plane_ddb[plane_id];
|
||||||
struct skl_ddb_entry *ddb_y =
|
struct skl_ddb_entry *ddb_y =
|
||||||
&crtc_state->wm.skl.plane_ddb_y[plane_id];
|
&crtc_state->wm.skl.plane_ddb_y[plane_id];
|
||||||
struct skl_ddb_entry *ddb_uv =
|
|
||||||
&crtc_state->wm.skl.plane_ddb_uv[plane_id];
|
|
||||||
|
|
||||||
skl_ddb_get_hw_plane_state(dev_priv, crtc->pipe,
|
skl_ddb_get_hw_plane_state(dev_priv, crtc->pipe,
|
||||||
plane_id, ddb_y, ddb_uv);
|
plane_id, ddb, ddb_y);
|
||||||
|
|
||||||
|
skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb);
|
||||||
skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb_y);
|
skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb_y);
|
||||||
skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb_uv);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
dbuf_state->weight[pipe] = intel_crtc_ddb_weight(crtc_state);
|
dbuf_state->weight[pipe] = intel_crtc_ddb_weight(crtc_state);
|
||||||
|
|
Loading…
Reference in New Issue