mmc: sdhci-omap: Add OMAP SDHCI driver
Create a new sdhci-omap driver to configure the eMMC/SD/SDIO controller in TI's OMAP SoCs making use of the SDHCI core library. For OMAP specific configurations, populate sdhci_ops with OMAP specific callbacks and use SDHCI quirks. Enable only high speed mode for both SD and eMMC here and add other UHS mode support later. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Kishon Vijay Abraham I
Ulf Hansson
parent
9ebd65cbdf
commit
7d326930d3
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@ -899,3 +899,15 @@ config MMC_SDHCI_XENON
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This selects Marvell Xenon eMMC/SD/SDIO SDHCI.
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If you have a controller with this interface, say Y or M here.
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If unsure, say N.
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config MMC_SDHCI_OMAP
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tristate "TI SDHCI Controller Support"
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depends on MMC_SDHCI_PLTFM && OF
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help
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This selects the Secure Digital Host Controller Interface (SDHCI)
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support present in TI's DRA7 SOCs. The controller supports
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SD/MMC/SDIO devices.
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If you have a controller with this interface, say Y or M here.
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If unsure, say N.
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@ -89,6 +89,7 @@ obj-$(CONFIG_MMC_SDHCI_MSM) += sdhci-msm.o
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obj-$(CONFIG_MMC_SDHCI_ST) += sdhci-st.o
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obj-$(CONFIG_MMC_SDHCI_MICROCHIP_PIC32) += sdhci-pic32.o
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obj-$(CONFIG_MMC_SDHCI_BRCMSTB) += sdhci-brcmstb.o
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obj-$(CONFIG_MMC_SDHCI_OMAP) += sdhci-omap.o
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ifeq ($(CONFIG_CB710_DEBUG),y)
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CFLAGS-cb710-mmc += -DDEBUG
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@ -0,0 +1,607 @@
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/**
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* SDHCI Controller driver for TI's OMAP SoCs
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*
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* Copyright (C) 2017 Texas Instruments
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* Author: Kishon Vijay Abraham I <kishon@ti.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 of
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* the License as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/delay.h>
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#include <linux/mmc/slot-gpio.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regulator/consumer.h>
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#include "sdhci-pltfm.h"
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#define SDHCI_OMAP_CON 0x12c
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#define CON_DW8 BIT(5)
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#define CON_DMA_MASTER BIT(20)
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#define CON_INIT BIT(1)
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#define CON_OD BIT(0)
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#define SDHCI_OMAP_CMD 0x20c
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#define SDHCI_OMAP_HCTL 0x228
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#define HCTL_SDBP BIT(8)
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#define HCTL_SDVS_SHIFT 9
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#define HCTL_SDVS_MASK (0x7 << HCTL_SDVS_SHIFT)
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#define HCTL_SDVS_33 (0x7 << HCTL_SDVS_SHIFT)
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#define HCTL_SDVS_30 (0x6 << HCTL_SDVS_SHIFT)
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#define HCTL_SDVS_18 (0x5 << HCTL_SDVS_SHIFT)
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#define SDHCI_OMAP_SYSCTL 0x22c
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#define SYSCTL_CEN BIT(2)
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#define SYSCTL_CLKD_SHIFT 6
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#define SYSCTL_CLKD_MASK 0x3ff
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#define SDHCI_OMAP_STAT 0x230
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#define SDHCI_OMAP_IE 0x234
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#define INT_CC_EN BIT(0)
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#define SDHCI_OMAP_AC12 0x23c
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#define AC12_V1V8_SIGEN BIT(19)
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#define SDHCI_OMAP_CAPA 0x240
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#define CAPA_VS33 BIT(24)
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#define CAPA_VS30 BIT(25)
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#define CAPA_VS18 BIT(26)
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#define SDHCI_OMAP_TIMEOUT 1 /* 1 msec */
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#define SYSCTL_CLKD_MAX 0x3FF
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#define IOV_1V8 1800000 /* 180000 uV */
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#define IOV_3V0 3000000 /* 300000 uV */
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#define IOV_3V3 3300000 /* 330000 uV */
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struct sdhci_omap_data {
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u32 offset;
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};
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struct sdhci_omap_host {
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void __iomem *base;
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struct device *dev;
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struct regulator *pbias;
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bool pbias_enabled;
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struct sdhci_host *host;
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u8 bus_mode;
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u8 power_mode;
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};
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static inline u32 sdhci_omap_readl(struct sdhci_omap_host *host,
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unsigned int offset)
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{
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return readl(host->base + offset);
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}
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static inline void sdhci_omap_writel(struct sdhci_omap_host *host,
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unsigned int offset, u32 data)
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{
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writel(data, host->base + offset);
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}
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static int sdhci_omap_set_pbias(struct sdhci_omap_host *omap_host,
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bool power_on, unsigned int iov)
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{
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int ret;
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struct device *dev = omap_host->dev;
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if (IS_ERR(omap_host->pbias))
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return 0;
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if (power_on) {
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ret = regulator_set_voltage(omap_host->pbias, iov, iov);
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if (ret) {
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dev_err(dev, "pbias set voltage failed\n");
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return ret;
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}
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if (omap_host->pbias_enabled)
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return 0;
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ret = regulator_enable(omap_host->pbias);
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if (ret) {
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dev_err(dev, "pbias reg enable fail\n");
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return ret;
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}
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omap_host->pbias_enabled = true;
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} else {
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if (!omap_host->pbias_enabled)
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return 0;
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ret = regulator_disable(omap_host->pbias);
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if (ret) {
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dev_err(dev, "pbias reg disable fail\n");
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return ret;
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}
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omap_host->pbias_enabled = false;
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}
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return 0;
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}
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static int sdhci_omap_enable_iov(struct sdhci_omap_host *omap_host,
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unsigned int iov)
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{
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int ret;
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struct sdhci_host *host = omap_host->host;
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struct mmc_host *mmc = host->mmc;
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ret = sdhci_omap_set_pbias(omap_host, false, 0);
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if (ret)
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return ret;
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if (!IS_ERR(mmc->supply.vqmmc)) {
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ret = regulator_set_voltage(mmc->supply.vqmmc, iov, iov);
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if (ret) {
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dev_err(mmc_dev(mmc), "vqmmc set voltage failed\n");
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return ret;
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}
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}
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ret = sdhci_omap_set_pbias(omap_host, true, iov);
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if (ret)
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return ret;
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return 0;
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}
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static void sdhci_omap_conf_bus_power(struct sdhci_omap_host *omap_host,
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unsigned char signal_voltage)
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{
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u32 reg;
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ktime_t timeout;
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reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL);
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reg &= ~HCTL_SDVS_MASK;
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if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
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reg |= HCTL_SDVS_33;
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else
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reg |= HCTL_SDVS_18;
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sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg);
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reg |= HCTL_SDBP;
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sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg);
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/* wait 1ms */
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timeout = ktime_add_ms(ktime_get(), SDHCI_OMAP_TIMEOUT);
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while (!(sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL) & HCTL_SDBP)) {
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if (WARN_ON(ktime_after(ktime_get(), timeout)))
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return;
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usleep_range(5, 10);
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}
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}
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static int sdhci_omap_start_signal_voltage_switch(struct mmc_host *mmc,
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struct mmc_ios *ios)
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{
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u32 reg;
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int ret;
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unsigned int iov;
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struct sdhci_host *host = mmc_priv(mmc);
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struct sdhci_pltfm_host *pltfm_host;
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struct sdhci_omap_host *omap_host;
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struct device *dev;
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pltfm_host = sdhci_priv(host);
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omap_host = sdhci_pltfm_priv(pltfm_host);
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dev = omap_host->dev;
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if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
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reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
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if (!(reg & CAPA_VS33))
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return -EOPNOTSUPP;
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sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage);
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reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
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reg &= ~AC12_V1V8_SIGEN;
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sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
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iov = IOV_3V3;
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} else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
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reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
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if (!(reg & CAPA_VS18))
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return -EOPNOTSUPP;
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sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage);
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reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
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reg |= AC12_V1V8_SIGEN;
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sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
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iov = IOV_1V8;
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} else {
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return -EOPNOTSUPP;
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}
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ret = sdhci_omap_enable_iov(omap_host, iov);
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if (ret) {
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dev_err(dev, "failed to switch IO voltage to %dmV\n", iov);
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return ret;
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}
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dev_dbg(dev, "IO voltage switched to %dmV\n", iov);
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return 0;
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}
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static void sdhci_omap_set_bus_mode(struct sdhci_omap_host *omap_host,
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unsigned int mode)
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{
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u32 reg;
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if (omap_host->bus_mode == mode)
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return;
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reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
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if (mode == MMC_BUSMODE_OPENDRAIN)
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reg |= CON_OD;
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else
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reg &= ~CON_OD;
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sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
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omap_host->bus_mode = mode;
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}
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void sdhci_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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{
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struct sdhci_host *host = mmc_priv(mmc);
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struct sdhci_pltfm_host *pltfm_host;
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struct sdhci_omap_host *omap_host;
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pltfm_host = sdhci_priv(host);
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omap_host = sdhci_pltfm_priv(pltfm_host);
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sdhci_omap_set_bus_mode(omap_host, ios->bus_mode);
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sdhci_set_ios(mmc, ios);
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}
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static u16 sdhci_omap_calc_divisor(struct sdhci_pltfm_host *host,
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unsigned int clock)
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{
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u16 dsor;
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dsor = DIV_ROUND_UP(clk_get_rate(host->clk), clock);
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if (dsor > SYSCTL_CLKD_MAX)
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dsor = SYSCTL_CLKD_MAX;
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return dsor;
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}
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static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host)
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{
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u32 reg;
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reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL);
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reg |= SYSCTL_CEN;
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sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg);
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}
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static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host)
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{
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u32 reg;
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reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL);
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reg &= ~SYSCTL_CEN;
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sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg);
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}
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static void sdhci_omap_set_clock(struct sdhci_host *host, unsigned int clock)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
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unsigned long clkdiv;
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sdhci_omap_stop_clock(omap_host);
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if (!clock)
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return;
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clkdiv = sdhci_omap_calc_divisor(pltfm_host, clock);
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clkdiv = (clkdiv & SYSCTL_CLKD_MASK) << SYSCTL_CLKD_SHIFT;
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sdhci_enable_clk(host, clkdiv);
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sdhci_omap_start_clock(omap_host);
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}
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void sdhci_omap_set_power(struct sdhci_host *host, unsigned char mode,
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unsigned short vdd)
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{
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struct mmc_host *mmc = host->mmc;
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mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
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}
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static int sdhci_omap_enable_dma(struct sdhci_host *host)
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{
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u32 reg;
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
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reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
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reg |= CON_DMA_MASTER;
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sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
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return 0;
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}
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unsigned int sdhci_omap_get_min_clock(struct sdhci_host *host)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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return clk_get_rate(pltfm_host->clk) / SYSCTL_CLKD_MAX;
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}
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static void sdhci_omap_set_bus_width(struct sdhci_host *host, int width)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
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u32 reg;
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reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
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if (width == MMC_BUS_WIDTH_8)
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reg |= CON_DW8;
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else
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reg &= ~CON_DW8;
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sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
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sdhci_set_bus_width(host, width);
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}
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static void sdhci_omap_init_74_clocks(struct sdhci_host *host, u8 power_mode)
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{
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u32 reg;
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ktime_t timeout;
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
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if (omap_host->power_mode == power_mode)
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return;
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if (power_mode != MMC_POWER_ON)
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return;
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disable_irq(host->irq);
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reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
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reg |= CON_INIT;
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sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
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sdhci_omap_writel(omap_host, SDHCI_OMAP_CMD, 0x0);
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/* wait 1ms */
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timeout = ktime_add_ms(ktime_get(), SDHCI_OMAP_TIMEOUT);
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while (!(sdhci_omap_readl(omap_host, SDHCI_OMAP_STAT) & INT_CC_EN)) {
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if (WARN_ON(ktime_after(ktime_get(), timeout)))
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return;
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usleep_range(5, 10);
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}
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reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
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reg &= ~CON_INIT;
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sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
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sdhci_omap_writel(omap_host, SDHCI_OMAP_STAT, INT_CC_EN);
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enable_irq(host->irq);
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omap_host->power_mode = power_mode;
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}
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static struct sdhci_ops sdhci_omap_ops = {
|
||||
.set_clock = sdhci_omap_set_clock,
|
||||
.set_power = sdhci_omap_set_power,
|
||||
.enable_dma = sdhci_omap_enable_dma,
|
||||
.get_max_clock = sdhci_pltfm_clk_get_max_clock,
|
||||
.get_min_clock = sdhci_omap_get_min_clock,
|
||||
.set_bus_width = sdhci_omap_set_bus_width,
|
||||
.platform_send_init_74_clocks = sdhci_omap_init_74_clocks,
|
||||
.reset = sdhci_reset,
|
||||
.set_uhs_signaling = sdhci_set_uhs_signaling,
|
||||
};
|
||||
|
||||
static int sdhci_omap_set_capabilities(struct sdhci_omap_host *omap_host)
|
||||
{
|
||||
u32 reg;
|
||||
int ret = 0;
|
||||
struct device *dev = omap_host->dev;
|
||||
struct regulator *vqmmc;
|
||||
|
||||
vqmmc = regulator_get(dev, "vqmmc");
|
||||
if (IS_ERR(vqmmc)) {
|
||||
ret = PTR_ERR(vqmmc);
|
||||
goto reg_put;
|
||||
}
|
||||
|
||||
/* voltage capabilities might be set by boot loader, clear it */
|
||||
reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
|
||||
reg &= ~(CAPA_VS18 | CAPA_VS30 | CAPA_VS33);
|
||||
|
||||
if (regulator_is_supported_voltage(vqmmc, IOV_3V3, IOV_3V3))
|
||||
reg |= CAPA_VS33;
|
||||
if (regulator_is_supported_voltage(vqmmc, IOV_1V8, IOV_1V8))
|
||||
reg |= CAPA_VS18;
|
||||
|
||||
sdhci_omap_writel(omap_host, SDHCI_OMAP_CAPA, reg);
|
||||
|
||||
reg_put:
|
||||
regulator_put(vqmmc);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct sdhci_pltfm_data sdhci_omap_pdata = {
|
||||
.quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
|
||||
SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
|
||||
SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
|
||||
SDHCI_QUIRK_NO_HISPD_BIT |
|
||||
SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
|
||||
.quirks2 = SDHCI_QUIRK2_NO_1_8_V |
|
||||
SDHCI_QUIRK2_ACMD23_BROKEN |
|
||||
SDHCI_QUIRK2_RSP_136_HAS_CRC,
|
||||
.ops = &sdhci_omap_ops,
|
||||
};
|
||||
|
||||
static const struct sdhci_omap_data dra7_data = {
|
||||
.offset = 0x200,
|
||||
};
|
||||
|
||||
static const struct of_device_id omap_sdhci_match[] = {
|
||||
{ .compatible = "ti,dra7-sdhci", .data = &dra7_data },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, omap_sdhci_match);
|
||||
|
||||
static int sdhci_omap_probe(struct platform_device *pdev)
|
||||
{
|
||||
int ret;
|
||||
u32 offset;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct sdhci_host *host;
|
||||
struct sdhci_pltfm_host *pltfm_host;
|
||||
struct sdhci_omap_host *omap_host;
|
||||
struct mmc_host *mmc;
|
||||
const struct of_device_id *match;
|
||||
struct sdhci_omap_data *data;
|
||||
|
||||
match = of_match_device(omap_sdhci_match, dev);
|
||||
if (!match)
|
||||
return -EINVAL;
|
||||
|
||||
data = (struct sdhci_omap_data *)match->data;
|
||||
if (!data) {
|
||||
dev_err(dev, "no sdhci omap data\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
offset = data->offset;
|
||||
|
||||
host = sdhci_pltfm_init(pdev, &sdhci_omap_pdata,
|
||||
sizeof(*omap_host));
|
||||
if (IS_ERR(host)) {
|
||||
dev_err(dev, "Failed sdhci_pltfm_init\n");
|
||||
return PTR_ERR(host);
|
||||
}
|
||||
|
||||
pltfm_host = sdhci_priv(host);
|
||||
omap_host = sdhci_pltfm_priv(pltfm_host);
|
||||
omap_host->host = host;
|
||||
omap_host->base = host->ioaddr;
|
||||
omap_host->dev = dev;
|
||||
host->ioaddr += offset;
|
||||
|
||||
mmc = host->mmc;
|
||||
ret = mmc_of_parse(mmc);
|
||||
if (ret)
|
||||
goto err_pltfm_free;
|
||||
|
||||
pltfm_host->clk = devm_clk_get(dev, "fck");
|
||||
if (IS_ERR(pltfm_host->clk)) {
|
||||
ret = PTR_ERR(pltfm_host->clk);
|
||||
goto err_pltfm_free;
|
||||
}
|
||||
|
||||
ret = clk_set_rate(pltfm_host->clk, mmc->f_max);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to set clock to %d\n", mmc->f_max);
|
||||
goto err_pltfm_free;
|
||||
}
|
||||
|
||||
omap_host->pbias = devm_regulator_get_optional(dev, "pbias");
|
||||
if (IS_ERR(omap_host->pbias)) {
|
||||
ret = PTR_ERR(omap_host->pbias);
|
||||
if (ret != -ENODEV)
|
||||
goto err_pltfm_free;
|
||||
dev_dbg(dev, "unable to get pbias regulator %d\n", ret);
|
||||
}
|
||||
omap_host->pbias_enabled = false;
|
||||
|
||||
/*
|
||||
* omap_device_pm_domain has callbacks to enable the main
|
||||
* functional clock, interface clock and also configure the
|
||||
* SYSCONFIG register of omap devices. The callback will be invoked
|
||||
* as part of pm_runtime_get_sync.
|
||||
*/
|
||||
pm_runtime_enable(dev);
|
||||
ret = pm_runtime_get_sync(dev);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "pm_runtime_get_sync failed\n");
|
||||
pm_runtime_put_noidle(dev);
|
||||
goto err_rpm_disable;
|
||||
}
|
||||
|
||||
ret = sdhci_omap_set_capabilities(omap_host);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to set system capabilities\n");
|
||||
goto err_put_sync;
|
||||
}
|
||||
|
||||
host->mmc_host_ops.get_ro = mmc_gpio_get_ro;
|
||||
host->mmc_host_ops.start_signal_voltage_switch =
|
||||
sdhci_omap_start_signal_voltage_switch;
|
||||
host->mmc_host_ops.set_ios = sdhci_omap_set_ios;
|
||||
|
||||
sdhci_read_caps(host);
|
||||
host->caps |= SDHCI_CAN_DO_ADMA2;
|
||||
|
||||
ret = sdhci_add_host(host);
|
||||
if (ret)
|
||||
goto err_put_sync;
|
||||
|
||||
return 0;
|
||||
|
||||
err_put_sync:
|
||||
pm_runtime_put_sync(dev);
|
||||
|
||||
err_rpm_disable:
|
||||
pm_runtime_disable(dev);
|
||||
|
||||
err_pltfm_free:
|
||||
sdhci_pltfm_free(pdev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int sdhci_omap_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct sdhci_host *host = platform_get_drvdata(pdev);
|
||||
|
||||
sdhci_remove_host(host, true);
|
||||
pm_runtime_put_sync(dev);
|
||||
pm_runtime_disable(dev);
|
||||
sdhci_pltfm_free(pdev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver sdhci_omap_driver = {
|
||||
.probe = sdhci_omap_probe,
|
||||
.remove = sdhci_omap_remove,
|
||||
.driver = {
|
||||
.name = "sdhci-omap",
|
||||
.of_match_table = omap_sdhci_match,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(sdhci_omap_driver);
|
||||
|
||||
MODULE_DESCRIPTION("SDHCI driver for OMAP SoCs");
|
||||
MODULE_AUTHOR("Texas Instruments Inc.");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_ALIAS("platform:sdhci_omap");
|
||||
Loading…
Reference in New Issue