Merge branch 'irqchip/mips' into irqchip/core
This commit is contained in:
Jason Cooper
commit
7cf03c9fe5
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@ -26,90 +26,6 @@
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#include "common.h"
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#include "machtypes.h"
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static void __init ath79_misc_intc_domain_init(
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struct device_node *node, int irq);
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static void ath79_misc_irq_handler(struct irq_desc *desc)
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{
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struct irq_domain *domain = irq_desc_get_handler_data(desc);
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void __iomem *base = domain->host_data;
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u32 pending;
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pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) &
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__raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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if (!pending) {
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spurious_interrupt();
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return;
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}
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while (pending) {
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int bit = __ffs(pending);
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generic_handle_irq(irq_linear_revmap(domain, bit));
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pending &= ~BIT(bit);
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}
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}
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static void ar71xx_misc_irq_unmask(struct irq_data *d)
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{
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void __iomem *base = irq_data_get_irq_chip_data(d);
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unsigned int irq = d->hwirq;
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u32 t;
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t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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__raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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/* flush write */
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__raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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}
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static void ar71xx_misc_irq_mask(struct irq_data *d)
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{
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void __iomem *base = irq_data_get_irq_chip_data(d);
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unsigned int irq = d->hwirq;
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u32 t;
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t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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__raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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/* flush write */
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__raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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}
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static void ar724x_misc_irq_ack(struct irq_data *d)
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{
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void __iomem *base = irq_data_get_irq_chip_data(d);
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unsigned int irq = d->hwirq;
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u32 t;
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t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
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__raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_STATUS);
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/* flush write */
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__raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
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}
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static struct irq_chip ath79_misc_irq_chip = {
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.name = "MISC",
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.irq_unmask = ar71xx_misc_irq_unmask,
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.irq_mask = ar71xx_misc_irq_mask,
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};
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static void __init ath79_misc_irq_init(void)
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{
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if (soc_is_ar71xx() || soc_is_ar913x())
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ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
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else if (soc_is_ar724x() ||
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soc_is_ar933x() ||
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soc_is_ar934x() ||
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soc_is_qca955x())
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ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
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else
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BUG();
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ath79_misc_intc_domain_init(NULL, ATH79_CPU_IRQ(6));
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}
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static void ar934x_ip2_irq_dispatch(struct irq_desc *desc)
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{
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@ -212,142 +128,12 @@ static void qca955x_irq_init(void)
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irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
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}
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/*
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* The IP2/IP3 lines are tied to a PCI/WMAC/USB device. Drivers for
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* these devices typically allocate coherent DMA memory, however the
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* DMA controller may still have some unsynchronized data in the FIFO.
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* Issue a flush in the handlers to ensure that the driver sees
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* the update.
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*
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* This array map the interrupt lines to the DDR write buffer channels.
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*/
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static unsigned irq_wb_chan[8] = {
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-1, -1, -1, -1, -1, -1, -1, -1,
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};
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned long pending;
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int irq;
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pending = read_c0_status() & read_c0_cause() & ST0_IM;
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if (!pending) {
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spurious_interrupt();
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return;
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}
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pending >>= CAUSEB_IP;
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while (pending) {
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irq = fls(pending) - 1;
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if (irq < ARRAY_SIZE(irq_wb_chan) && irq_wb_chan[irq] != -1)
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ath79_ddr_wb_flush(irq_wb_chan[irq]);
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do_IRQ(MIPS_CPU_IRQ_BASE + irq);
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pending &= ~BIT(irq);
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}
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}
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static int misc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
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{
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irq_set_chip_and_handler(irq, &ath79_misc_irq_chip, handle_level_irq);
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irq_set_chip_data(irq, d->host_data);
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return 0;
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}
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static const struct irq_domain_ops misc_irq_domain_ops = {
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.xlate = irq_domain_xlate_onecell,
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.map = misc_map,
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};
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static void __init ath79_misc_intc_domain_init(
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struct device_node *node, int irq)
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{
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void __iomem *base = ath79_reset_base;
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struct irq_domain *domain;
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domain = irq_domain_add_legacy(node, ATH79_MISC_IRQ_COUNT,
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ATH79_MISC_IRQ_BASE, 0, &misc_irq_domain_ops, base);
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if (!domain)
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panic("Failed to add MISC irqdomain");
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/* Disable and clear all interrupts */
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__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
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irq_set_chained_handler_and_data(irq, ath79_misc_irq_handler, domain);
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}
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static int __init ath79_misc_intc_of_init(
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struct device_node *node, struct device_node *parent)
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{
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int irq;
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irq = irq_of_parse_and_map(node, 0);
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if (!irq)
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panic("Failed to get MISC IRQ");
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ath79_misc_intc_domain_init(node, irq);
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return 0;
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}
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static int __init ar7100_misc_intc_of_init(
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struct device_node *node, struct device_node *parent)
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{
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ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
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return ath79_misc_intc_of_init(node, parent);
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}
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IRQCHIP_DECLARE(ar7100_misc_intc, "qca,ar7100-misc-intc",
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ar7100_misc_intc_of_init);
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static int __init ar7240_misc_intc_of_init(
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struct device_node *node, struct device_node *parent)
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{
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ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
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return ath79_misc_intc_of_init(node, parent);
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}
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IRQCHIP_DECLARE(ar7240_misc_intc, "qca,ar7240-misc-intc",
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ar7240_misc_intc_of_init);
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static int __init ar79_cpu_intc_of_init(
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struct device_node *node, struct device_node *parent)
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{
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int err, i, count;
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/* Fill the irq_wb_chan table */
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count = of_count_phandle_with_args(
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node, "qca,ddr-wb-channels", "#qca,ddr-wb-channel-cells");
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for (i = 0; i < count; i++) {
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struct of_phandle_args args;
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u32 irq = i;
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of_property_read_u32_index(
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node, "qca,ddr-wb-channel-interrupts", i, &irq);
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if (irq >= ARRAY_SIZE(irq_wb_chan))
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continue;
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err = of_parse_phandle_with_args(
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node, "qca,ddr-wb-channels",
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"#qca,ddr-wb-channel-cells",
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i, &args);
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if (err)
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return err;
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irq_wb_chan[irq] = args.args[0];
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pr_info("IRQ: Set flush channel of IRQ%d to %d\n",
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irq, args.args[0]);
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}
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return mips_cpu_irq_of_init(node, parent);
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}
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IRQCHIP_DECLARE(ar79_cpu_intc, "qca,ar7100-cpu-intc",
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ar79_cpu_intc_of_init);
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void __init arch_init_irq(void)
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{
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unsigned irq_wb_chan2 = -1;
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unsigned irq_wb_chan3 = -1;
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bool misc_is_ar71xx;
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if (mips_machtype == ATH79_MACH_GENERIC_OF) {
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irqchip_init();
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return;
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@ -355,14 +141,26 @@ void __init arch_init_irq(void)
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if (soc_is_ar71xx() || soc_is_ar724x() ||
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soc_is_ar913x() || soc_is_ar933x()) {
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irq_wb_chan[2] = 3;
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irq_wb_chan[3] = 2;
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irq_wb_chan2 = 3;
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irq_wb_chan3 = 2;
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} else if (soc_is_ar934x()) {
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irq_wb_chan[3] = 2;
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irq_wb_chan3 = 2;
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}
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mips_cpu_irq_init();
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ath79_misc_irq_init();
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ath79_cpu_irq_init(irq_wb_chan2, irq_wb_chan3);
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if (soc_is_ar71xx() || soc_is_ar913x())
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misc_is_ar71xx = true;
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else if (soc_is_ar724x() ||
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soc_is_ar933x() ||
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soc_is_ar934x() ||
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soc_is_qca955x())
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misc_is_ar71xx = false;
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else
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BUG();
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ath79_misc_irq_init(
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ath79_reset_base + AR71XX_RESET_REG_MISC_INT_STATUS,
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ATH79_CPU_IRQ(6), ATH79_MISC_IRQ_BASE, misc_is_ar71xx);
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if (soc_is_ar934x())
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ar934x_ip2_irq_init();
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|
|
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@ -144,4 +144,8 @@ static inline u32 ath79_reset_rr(unsigned reg)
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void ath79_device_reset_set(u32 mask);
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void ath79_device_reset_clear(u32 mask);
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void ath79_cpu_irq_init(unsigned irq_wb_chan2, unsigned irq_wb_chan3);
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void ath79_misc_irq_init(void __iomem *regs, int irq,
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int irq_base, bool is_ar71xx);
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#endif /* __ASM_MACH_ATH79_H */
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|
|
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|
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@ -1,5 +1,7 @@
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obj-$(CONFIG_IRQCHIP) += irqchip.o
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obj-$(CONFIG_ATH79) += irq-ath79-cpu.o
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obj-$(CONFIG_ATH79) += irq-ath79-misc.o
|
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obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
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obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
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obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o
|
||||
|
|
|
|||
|
|
@ -0,0 +1,97 @@
|
|||
/*
|
||||
* Atheros AR71xx/AR724x/AR913x specific interrupt handling
|
||||
*
|
||||
* Copyright (C) 2015 Alban Bedel <albeu@free.fr>
|
||||
* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
|
||||
* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
|
||||
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||
*
|
||||
* Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
#include <asm/irq_cpu.h>
|
||||
#include <asm/mach-ath79/ath79.h>
|
||||
|
||||
/*
|
||||
* The IP2/IP3 lines are tied to a PCI/WMAC/USB device. Drivers for
|
||||
* these devices typically allocate coherent DMA memory, however the
|
||||
* DMA controller may still have some unsynchronized data in the FIFO.
|
||||
* Issue a flush in the handlers to ensure that the driver sees
|
||||
* the update.
|
||||
*
|
||||
* This array map the interrupt lines to the DDR write buffer channels.
|
||||
*/
|
||||
|
||||
static unsigned irq_wb_chan[8] = {
|
||||
-1, -1, -1, -1, -1, -1, -1, -1,
|
||||
};
|
||||
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned long pending;
|
||||
int irq;
|
||||
|
||||
pending = read_c0_status() & read_c0_cause() & ST0_IM;
|
||||
|
||||
if (!pending) {
|
||||
spurious_interrupt();
|
||||
return;
|
||||
}
|
||||
|
||||
pending >>= CAUSEB_IP;
|
||||
while (pending) {
|
||||
irq = fls(pending) - 1;
|
||||
if (irq < ARRAY_SIZE(irq_wb_chan) && irq_wb_chan[irq] != -1)
|
||||
ath79_ddr_wb_flush(irq_wb_chan[irq]);
|
||||
do_IRQ(MIPS_CPU_IRQ_BASE + irq);
|
||||
pending &= ~BIT(irq);
|
||||
}
|
||||
}
|
||||
|
||||
static int __init ar79_cpu_intc_of_init(
|
||||
struct device_node *node, struct device_node *parent)
|
||||
{
|
||||
int err, i, count;
|
||||
|
||||
/* Fill the irq_wb_chan table */
|
||||
count = of_count_phandle_with_args(
|
||||
node, "qca,ddr-wb-channels", "#qca,ddr-wb-channel-cells");
|
||||
|
||||
for (i = 0; i < count; i++) {
|
||||
struct of_phandle_args args;
|
||||
u32 irq = i;
|
||||
|
||||
of_property_read_u32_index(
|
||||
node, "qca,ddr-wb-channel-interrupts", i, &irq);
|
||||
if (irq >= ARRAY_SIZE(irq_wb_chan))
|
||||
continue;
|
||||
|
||||
err = of_parse_phandle_with_args(
|
||||
node, "qca,ddr-wb-channels",
|
||||
"#qca,ddr-wb-channel-cells",
|
||||
i, &args);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
irq_wb_chan[irq] = args.args[0];
|
||||
}
|
||||
|
||||
return mips_cpu_irq_of_init(node, parent);
|
||||
}
|
||||
IRQCHIP_DECLARE(ar79_cpu_intc, "qca,ar7100-cpu-intc",
|
||||
ar79_cpu_intc_of_init);
|
||||
|
||||
void __init ath79_cpu_irq_init(unsigned irq_wb_chan2, unsigned irq_wb_chan3)
|
||||
{
|
||||
irq_wb_chan[2] = irq_wb_chan2;
|
||||
irq_wb_chan[3] = irq_wb_chan3;
|
||||
mips_cpu_irq_init();
|
||||
}
|
||||
|
|
@ -0,0 +1,189 @@
|
|||
/*
|
||||
* Atheros AR71xx/AR724x/AR913x MISC interrupt controller
|
||||
*
|
||||
* Copyright (C) 2015 Alban Bedel <albeu@free.fr>
|
||||
* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
|
||||
* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
|
||||
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||
*
|
||||
* Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/irqchip/chained_irq.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
|
||||
#define AR71XX_RESET_REG_MISC_INT_STATUS 0
|
||||
#define AR71XX_RESET_REG_MISC_INT_ENABLE 4
|
||||
|
||||
#define ATH79_MISC_IRQ_COUNT 32
|
||||
|
||||
static void ath79_misc_irq_handler(struct irq_desc *desc)
|
||||
{
|
||||
struct irq_domain *domain = irq_desc_get_handler_data(desc);
|
||||
struct irq_chip *chip = irq_desc_get_chip(desc);
|
||||
void __iomem *base = domain->host_data;
|
||||
u32 pending;
|
||||
|
||||
chained_irq_enter(chip, desc);
|
||||
|
||||
pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) &
|
||||
__raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
|
||||
|
||||
if (!pending) {
|
||||
spurious_interrupt();
|
||||
chained_irq_exit(chip, desc);
|
||||
return;
|
||||
}
|
||||
|
||||
while (pending) {
|
||||
int bit = __ffs(pending);
|
||||
|
||||
generic_handle_irq(irq_linear_revmap(domain, bit));
|
||||
pending &= ~BIT(bit);
|
||||
}
|
||||
|
||||
chained_irq_exit(chip, desc);
|
||||
}
|
||||
|
||||
static void ar71xx_misc_irq_unmask(struct irq_data *d)
|
||||
{
|
||||
void __iomem *base = irq_data_get_irq_chip_data(d);
|
||||
unsigned int irq = d->hwirq;
|
||||
u32 t;
|
||||
|
||||
t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
|
||||
__raw_writel(t | BIT(irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
|
||||
|
||||
/* flush write */
|
||||
__raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
|
||||
}
|
||||
|
||||
static void ar71xx_misc_irq_mask(struct irq_data *d)
|
||||
{
|
||||
void __iomem *base = irq_data_get_irq_chip_data(d);
|
||||
unsigned int irq = d->hwirq;
|
||||
u32 t;
|
||||
|
||||
t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
|
||||
__raw_writel(t & ~BIT(irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
|
||||
|
||||
/* flush write */
|
||||
__raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
|
||||
}
|
||||
|
||||
static void ar724x_misc_irq_ack(struct irq_data *d)
|
||||
{
|
||||
void __iomem *base = irq_data_get_irq_chip_data(d);
|
||||
unsigned int irq = d->hwirq;
|
||||
u32 t;
|
||||
|
||||
t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
|
||||
__raw_writel(t & ~BIT(irq), base + AR71XX_RESET_REG_MISC_INT_STATUS);
|
||||
|
||||
/* flush write */
|
||||
__raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
|
||||
}
|
||||
|
||||
static struct irq_chip ath79_misc_irq_chip = {
|
||||
.name = "MISC",
|
||||
.irq_unmask = ar71xx_misc_irq_unmask,
|
||||
.irq_mask = ar71xx_misc_irq_mask,
|
||||
};
|
||||
|
||||
static int misc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
|
||||
{
|
||||
irq_set_chip_and_handler(irq, &ath79_misc_irq_chip, handle_level_irq);
|
||||
irq_set_chip_data(irq, d->host_data);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct irq_domain_ops misc_irq_domain_ops = {
|
||||
.xlate = irq_domain_xlate_onecell,
|
||||
.map = misc_map,
|
||||
};
|
||||
|
||||
static void __init ath79_misc_intc_domain_init(
|
||||
struct irq_domain *domain, int irq)
|
||||
{
|
||||
void __iomem *base = domain->host_data;
|
||||
|
||||
/* Disable and clear all interrupts */
|
||||
__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
|
||||
__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
|
||||
|
||||
irq_set_chained_handler_and_data(irq, ath79_misc_irq_handler, domain);
|
||||
}
|
||||
|
||||
static int __init ath79_misc_intc_of_init(
|
||||
struct device_node *node, struct device_node *parent)
|
||||
{
|
||||
struct irq_domain *domain;
|
||||
void __iomem *base;
|
||||
int irq;
|
||||
|
||||
irq = irq_of_parse_and_map(node, 0);
|
||||
if (!irq) {
|
||||
pr_err("Failed to get MISC IRQ\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
base = of_iomap(node, 0);
|
||||
if (!base) {
|
||||
pr_err("Failed to get MISC IRQ registers\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
domain = irq_domain_add_linear(node, ATH79_MISC_IRQ_COUNT,
|
||||
&misc_irq_domain_ops, base);
|
||||
if (!domain) {
|
||||
pr_err("Failed to add MISC irqdomain\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ath79_misc_intc_domain_init(domain, irq);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init ar7100_misc_intc_of_init(
|
||||
struct device_node *node, struct device_node *parent)
|
||||
{
|
||||
ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
|
||||
return ath79_misc_intc_of_init(node, parent);
|
||||
}
|
||||
|
||||
IRQCHIP_DECLARE(ar7100_misc_intc, "qca,ar7100-misc-intc",
|
||||
ar7100_misc_intc_of_init);
|
||||
|
||||
static int __init ar7240_misc_intc_of_init(
|
||||
struct device_node *node, struct device_node *parent)
|
||||
{
|
||||
ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
|
||||
return ath79_misc_intc_of_init(node, parent);
|
||||
}
|
||||
|
||||
IRQCHIP_DECLARE(ar7240_misc_intc, "qca,ar7240-misc-intc",
|
||||
ar7240_misc_intc_of_init);
|
||||
|
||||
void __init ath79_misc_irq_init(void __iomem *regs, int irq,
|
||||
int irq_base, bool is_ar71xx)
|
||||
{
|
||||
struct irq_domain *domain;
|
||||
|
||||
if (is_ar71xx)
|
||||
ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
|
||||
else
|
||||
ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
|
||||
|
||||
domain = irq_domain_add_legacy(NULL, ATH79_MISC_IRQ_COUNT,
|
||||
irq_base, 0, &misc_irq_domain_ops, regs);
|
||||
if (!domain)
|
||||
panic("Failed to create MISC irqdomain");
|
||||
|
||||
ath79_misc_intc_domain_init(domain, irq);
|
||||
}
|
||||
Loading…
Reference in New Issue