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Merge remote-tracking branch 'acme/perf-tools' into perf-tools-next 

To pick up fixes that were already merged upstream.

Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Arnaldo Carvalho de Melo 2023-05-22 15:22:46 -03:00
parent a9650b7f6f 4e111f0cf0
commit 7cdda6998e
22 changed files with 354 additions and 289 deletions
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26
tools/arch/x86/include/asm/cpufeatures.h
View File

@ -97,7 +97,7 @@
#define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in IA32 userspace */
#define X86_FEATURE_REP_GOOD ( 3*32+16) /* REP microcode works well */
#define X86_FEATURE_AMD_LBR_V2 ( 3*32+17) /* AMD Last Branch Record Extension Version 2 */
#define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" LFENCE synchronizes RDTSC */
/* FREE, was #define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) "" LFENCE synchronizes RDTSC */
#define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */
#define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */
#define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */
@ -226,10 +226,9 @@
/* Virtualization flags: Linux defined, word 8 */
#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */
#define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */
#define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */
#define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */
#define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */
#define X86_FEATURE_FLEXPRIORITY ( 8*32+ 1) /* Intel FlexPriority */
#define X86_FEATURE_EPT ( 8*32+ 2) /* Intel Extended Page Table */
#define X86_FEATURE_VPID ( 8*32+ 3) /* Intel Virtual Processor ID */
#define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer VMMCALL to VMCALL */
#define X86_FEATURE_XENPV ( 8*32+16) /* "" Xen paravirtual guest */
@ -307,14 +306,21 @@
#define X86_FEATURE_SGX_EDECCSSA (11*32+18) /* "" SGX EDECCSSA user leaf function */
#define X86_FEATURE_CALL_DEPTH (11*32+19) /* "" Call depth tracking for RSB stuffing */
#define X86_FEATURE_MSR_TSX_CTRL (11*32+20) /* "" MSR IA32_TSX_CTRL (Intel) implemented */
#define X86_FEATURE_SMBA (11*32+21) /* "" Slow Memory Bandwidth Allocation */
#define X86_FEATURE_BMEC (11*32+22) /* "" Bandwidth Monitoring Event Configuration */
/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
#define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */
#define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */
#define X86_FEATURE_CMPCCXADD (12*32+ 7) /* "" CMPccXADD instructions */
#define X86_FEATURE_ARCH_PERFMON_EXT (12*32+ 8) /* "" Intel Architectural PerfMon Extension */
#define X86_FEATURE_FZRM (12*32+10) /* "" Fast zero-length REP MOVSB */
#define X86_FEATURE_FSRS (12*32+11) /* "" Fast short REP STOSB */
#define X86_FEATURE_FSRC (12*32+12) /* "" Fast short REP {CMPSB,SCASB} */
#define X86_FEATURE_LKGS (12*32+18) /* "" Load "kernel" (userspace) GS */
#define X86_FEATURE_AMX_FP16 (12*32+21) /* "" AMX fp16 Support */
#define X86_FEATURE_AVX_IFMA (12*32+23) /* "" Support for VPMADD52[H,L]UQ */
#define X86_FEATURE_LAM (12*32+26) /* Linear Address Masking */
/* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
#define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */
@ -331,6 +337,7 @@
#define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */
#define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */
#define X86_FEATURE_CPPC (13*32+27) /* Collaborative Processor Performance Control */
#define X86_FEATURE_AMD_PSFD (13*32+28) /* "" Predictive Store Forwarding Disable */
#define X86_FEATURE_BTC_NO (13*32+29) /* "" Not vulnerable to Branch Type Confusion */
#define X86_FEATURE_BRS (13*32+31) /* Branch Sampling available */
@ -363,6 +370,7 @@
#define X86_FEATURE_VGIF (15*32+16) /* Virtual GIF */
#define X86_FEATURE_X2AVIC (15*32+18) /* Virtual x2apic */
#define X86_FEATURE_V_SPEC_CTRL (15*32+20) /* Virtual SPEC_CTRL */
#define X86_FEATURE_VNMI (15*32+25) /* Virtual NMI */
#define X86_FEATURE_SVME_ADDR_CHK (15*32+28) /* "" SVME addr check */
/* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */
@ -427,6 +435,13 @@
#define X86_FEATURE_V_TSC_AUX (19*32+ 9) /* "" Virtual TSC_AUX */
#define X86_FEATURE_SME_COHERENT (19*32+10) /* "" AMD hardware-enforced cache coherency */
/* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */
#define X86_FEATURE_NO_NESTED_DATA_BP (20*32+ 0) /* "" No Nested Data Breakpoints */
#define X86_FEATURE_LFENCE_RDTSC (20*32+ 2) /* "" LFENCE always serializing / synchronizes RDTSC */
#define X86_FEATURE_NULL_SEL_CLR_BASE (20*32+ 6) /* "" Null Selector Clears Base */
#define X86_FEATURE_AUTOIBRS (20*32+ 8) /* "" Automatic IBRS */
#define X86_FEATURE_NO_SMM_CTL_MSR (20*32+ 9) /* "" SMM_CTL MSR is not present */
/*
* BUG word(s)
*/
@ -467,5 +482,6 @@
#define X86_BUG_MMIO_UNKNOWN X86_BUG(26) /* CPU is too old and its MMIO Stale Data status is unknown */
#define X86_BUG_RETBLEED X86_BUG(27) /* CPU is affected by RETBleed */
#define X86_BUG_EIBRS_PBRSB X86_BUG(28) /* EIBRS is vulnerable to Post Barrier RSB Predictions */
#define X86_BUG_SMT_RSB X86_BUG(29) /* CPU is vulnerable to Cross-Thread Return Address Predictions */
#endif /* _ASM_X86_CPUFEATURES_H */

8
tools/arch/x86/include/asm/disabled-features.h
View File

@ -75,6 +75,12 @@
# define DISABLE_CALL_DEPTH_TRACKING (1 << (X86_FEATURE_CALL_DEPTH & 31))
#endif
#ifdef CONFIG_ADDRESS_MASKING
# define DISABLE_LAM 0
#else
# define DISABLE_LAM (1 << (X86_FEATURE_LAM & 31))
#endif
#ifdef CONFIG_INTEL_IOMMU_SVM
# define DISABLE_ENQCMD 0
#else
@ -115,7 +121,7 @@
#define DISABLED_MASK10 0
#define DISABLED_MASK11 (DISABLE_RETPOLINE|DISABLE_RETHUNK|DISABLE_UNRET| \
DISABLE_CALL_DEPTH_TRACKING)
#define DISABLED_MASK12 0
#define DISABLED_MASK12 (DISABLE_LAM)
#define DISABLED_MASK13 0
#define DISABLED_MASK14 0
#define DISABLED_MASK15 0

8
tools/arch/x86/include/uapi/asm/prctl.h
View File

@ -16,8 +16,16 @@
#define ARCH_GET_XCOMP_GUEST_PERM 0x1024
#define ARCH_REQ_XCOMP_GUEST_PERM 0x1025
#define ARCH_XCOMP_TILECFG 17
#define ARCH_XCOMP_TILEDATA 18
#define ARCH_MAP_VDSO_X32 0x2001
#define ARCH_MAP_VDSO_32 0x2002
#define ARCH_MAP_VDSO_64 0x2003
#define ARCH_GET_UNTAG_MASK 0x4001
#define ARCH_ENABLE_TAGGED_ADDR 0x4002
#define ARCH_GET_MAX_TAG_BITS 0x4003
#define ARCH_FORCE_TAGGED_SVA 0x4004
#endif /* _ASM_X86_PRCTL_H */

3
tools/arch/x86/include/uapi/asm/unistd_32.h
View File

@ -2,6 +2,9 @@
#ifndef __NR_fork
#define __NR_fork 2
#endif
#ifndef __NR_execve
#define __NR_execve 11
#endif
#ifndef __NR_getppid
#define __NR_getppid 64
#endif

34
tools/arch/x86/lib/memcpy_64.S
View File

@ -9,13 +9,6 @@
.section .noinstr.text, "ax"
/*
* We build a jump to memcpy_orig by default which gets NOPped out on
* the majority of x86 CPUs which set REP_GOOD. In addition, CPUs which
* have the enhanced REP MOVSB/STOSB feature (ERMS), change those NOPs
* to a jmp to memcpy_erms which does the REP; MOVSB mem copy.
*/
/*
* memcpy - Copy a memory block.
*
@ -26,17 +19,21 @@
*
* Output:
* rax original destination
*
* The FSRM alternative should be done inline (avoiding the call and
* the disgusting return handling), but that would require some help
* from the compiler for better calling conventions.
*
* The 'rep movsb' itself is small enough to replace the call, but the
* two register moves blow up the code. And one of them is "needed"
* only for the return value that is the same as the source input,
* which the compiler could/should do much better anyway.
*/
SYM_TYPED_FUNC_START(__memcpy)
ALTERNATIVE_2 "jmp memcpy_orig", "", X86_FEATURE_REP_GOOD, \
"jmp memcpy_erms", X86_FEATURE_ERMS
ALTERNATIVE "jmp memcpy_orig", "", X86_FEATURE_FSRM
movq %rdi, %rax
movq %rdx, %rcx
shrq $3, %rcx
andl $7, %edx
rep movsq
movl %edx, %ecx
rep movsb
RET
SYM_FUNC_END(__memcpy)
@ -45,17 +42,6 @@ EXPORT_SYMBOL(__memcpy)
SYM_FUNC_ALIAS(memcpy, __memcpy)
EXPORT_SYMBOL(memcpy)
/*
* memcpy_erms() - enhanced fast string memcpy. This is faster and
* simpler than memcpy. Use memcpy_erms when possible.
*/
SYM_FUNC_START_LOCAL(memcpy_erms)
movq %rdi, %rax
movq %rdx, %rcx
rep movsb
RET
SYM_FUNC_END(memcpy_erms)
SYM_FUNC_START_LOCAL(memcpy_orig)
movq %rdi, %rax

47
tools/arch/x86/lib/memset_64.S
View File

@ -18,27 +18,22 @@
* rdx count (bytes)
*
* rax original destination
*
* The FSRS alternative should be done inline (avoiding the call and
* the disgusting return handling), but that would require some help
* from the compiler for better calling conventions.
*
* The 'rep stosb' itself is small enough to replace the call, but all
* the register moves blow up the code. And two of them are "needed"
* only for the return value that is the same as the source input,
* which the compiler could/should do much better anyway.
*/
SYM_FUNC_START(__memset)
/*
* Some CPUs support enhanced REP MOVSB/STOSB feature. It is recommended
* to use it when possible. If not available, use fast string instructions.
*
* Otherwise, use original memset function.
*/
ALTERNATIVE_2 "jmp memset_orig", "", X86_FEATURE_REP_GOOD, \
"jmp memset_erms", X86_FEATURE_ERMS
ALTERNATIVE "jmp memset_orig", "", X86_FEATURE_FSRS
movq %rdi,%r9
movb %sil,%al
movq %rdx,%rcx
andl $7,%edx
shrq $3,%rcx
/* expand byte value */
movzbl %sil,%esi
movabs $0x0101010101010101,%rax
imulq %rsi,%rax
rep stosq
movl %edx,%ecx
rep stosb
movq %r9,%rax
RET
@ -48,26 +43,6 @@ EXPORT_SYMBOL(__memset)
SYM_FUNC_ALIAS(memset, __memset)
EXPORT_SYMBOL(memset)
/*
* ISO C memset - set a memory block to a byte value. This function uses
* enhanced rep stosb to override the fast string function.
* The code is simpler and shorter than the fast string function as well.
*
* rdi destination
* rsi value (char)
* rdx count (bytes)
*
* rax original destination
*/
SYM_FUNC_START_LOCAL(memset_erms)
movq %rdi,%r9
movb %sil,%al
movq %rdx,%rcx
rep stosb
movq %r9,%rax
RET
SYM_FUNC_END(memset_erms)
SYM_FUNC_START_LOCAL(memset_orig)
movq %rdi,%r10

3
tools/include/asm/alternative.h
View File

@ -4,7 +4,6 @@
/* Just disable it so we can build arch/x86/lib/memcpy_64.S for perf bench: */
#define altinstruction_entry #
#define ALTERNATIVE_2 #
#define ALTERNATIVE #
#endif

2
tools/include/uapi/linux/prctl.h
View File

@ -290,6 +290,8 @@ struct prctl_mm_map {
#define PR_SET_VMA 0x53564d41
# define PR_SET_VMA_ANON_NAME 0
#define PR_GET_AUXV 0x41555856
#define PR_SET_MEMORY_MERGE 67
#define PR_GET_MEMORY_MERGE 68
#endif /* _LINUX_PRCTL_H */

2
tools/perf/arch/s390/entry/syscalls/syscall.tbl
View File

@ -449,7 +449,7 @@
444 common landlock_create_ruleset sys_landlock_create_ruleset sys_landlock_create_ruleset
445 common landlock_add_rule sys_landlock_add_rule sys_landlock_add_rule
446 common landlock_restrict_self sys_landlock_restrict_self sys_landlock_restrict_self
# 447 reserved for memfd_secret
447 common memfd_secret sys_memfd_secret sys_memfd_secret
448 common process_mrelease sys_process_mrelease sys_process_mrelease
449 common futex_waitv sys_futex_waitv sys_futex_waitv
450 common set_mempolicy_home_node sys_set_mempolicy_home_node sys_set_mempolicy_home_node

4
tools/perf/bench/mem-memcpy-x86-64-asm-def.h
View File

@ -7,7 +7,3 @@ MEMCPY_FN(memcpy_orig,
MEMCPY_FN(__memcpy,
"x86-64-movsq",
"movsq-based memcpy() in arch/x86/lib/memcpy_64.S")
MEMCPY_FN(memcpy_erms,
"x86-64-movsb",
"movsb-based memcpy() in arch/x86/lib/memcpy_64.S")

2
tools/perf/bench/mem-memcpy-x86-64-asm.S
View File

@ -2,7 +2,7 @@
/* Various wrappers to make the kernel .S file build in user-space: */
// memcpy_orig and memcpy_erms are being defined as SYM_L_LOCAL but we need it
// memcpy_orig is being defined as SYM_L_LOCAL but we need it
#define SYM_FUNC_START_LOCAL(name) \
SYM_START(name, SYM_L_GLOBAL, SYM_A_ALIGN)
#define memcpy MEMCPY /* don't hide glibc's memcpy() */

4
tools/perf/bench/mem-memset-x86-64-asm-def.h
View File

@ -7,7 +7,3 @@ MEMSET_FN(memset_orig,
MEMSET_FN(__memset,
"x86-64-stosq",
"movsq-based memset() in arch/x86/lib/memset_64.S")
MEMSET_FN(memset_erms,
"x86-64-stosb",
"movsb-based memset() in arch/x86/lib/memset_64.S")

2
tools/perf/bench/mem-memset-x86-64-asm.S
View File

@ -1,5 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0 */
// memset_orig and memset_erms are being defined as SYM_L_LOCAL but we need it
// memset_orig is being defined as SYM_L_LOCAL but we need it
#define SYM_FUNC_START_LOCAL(name) \
SYM_START(name, SYM_L_GLOBAL, SYM_A_ALIGN)
#define memset MEMSET /* don't hide glibc's memset() */

6
tools/perf/tests/attr.py
View File

@ -152,7 +152,7 @@ def parse_version(version):
# - expected values assignments
class Test(object):
def __init__(self, path, options):
parser = configparser.SafeConfigParser()
parser = configparser.ConfigParser()
parser.read(path)
log.warning("running '%s'" % path)
@ -247,7 +247,7 @@ class Test(object):
return True
def load_events(self, path, events):
parser_event = configparser.SafeConfigParser()
parser_event = configparser.ConfigParser()
parser_event.read(path)
# The event record section header contains 'event' word,
@ -261,7 +261,7 @@ class Test(object):
# Read parent event if there's any
if (':' in section):
base = section[section.index(':') + 1:]
parser_base = configparser.SafeConfigParser()
parser_base = configparser.ConfigParser()
parser_base.read(self.test_dir + '/' + base)
base_items = parser_base.items('event')

2
tools/perf/tests/attr/base-stat
View File

@ -16,7 +16,7 @@ pinned=0
exclusive=0
exclude_user=0
exclude_kernel=0|1
exclude_hv=0
exclude_hv=0|1
exclude_idle=0
mmap=0
comm=0

96
tools/perf/tests/attr/test-stat-default
View File

@ -40,7 +40,6 @@ fd=6
type=0
config=7
optional=1
# PERF_TYPE_HARDWARE / PERF_COUNT_HW_STALLED_CYCLES_BACKEND
[event7:base-stat]
fd=7
@ -89,22 +88,11 @@ enable_on_exec=0
read_format=15
optional=1
# PERF_TYPE_RAW / topdown-bad-spec (0x8100)
# PERF_TYPE_RAW / topdown-fe-bound (0x8200)
[event13:base-stat]
fd=13
group_fd=11
type=4
config=33024
disabled=0
enable_on_exec=0
read_format=15
optional=1
# PERF_TYPE_RAW / topdown-fe-bound (0x8200)
[event14:base-stat]
fd=14
group_fd=11
type=4
config=33280
disabled=0
enable_on_exec=0
@ -112,8 +100,8 @@ read_format=15
optional=1
# PERF_TYPE_RAW / topdown-be-bound (0x8300)
[event15:base-stat]
fd=15
[event14:base-stat]
fd=14
group_fd=11
type=4
config=33536
@ -122,46 +110,76 @@ enable_on_exec=0
read_format=15
optional=1
# PERF_TYPE_RAW / topdown-heavy-ops (0x8400)
# PERF_TYPE_RAW / topdown-bad-spec (0x8100)
[event15:base-stat]
fd=15
group_fd=11
type=4
config=33024
disabled=0
enable_on_exec=0
read_format=15
optional=1
# PERF_TYPE_RAW / INT_MISC.UOP_DROPPING
[event16:base-stat]
fd=16
group_fd=11
type=4
config=33792
disabled=0
enable_on_exec=0
read_format=15
config=4109
optional=1
# PERF_TYPE_RAW / topdown-br-mispredict (0x8500)
# PERF_TYPE_RAW / cpu/INT_MISC.RECOVERY_CYCLES,cmask=1,edge/
[event17:base-stat]
fd=17
group_fd=11
type=4
config=34048
disabled=0
enable_on_exec=0
read_format=15
config=17039629
optional=1
# PERF_TYPE_RAW / topdown-fetch-lat (0x8600)
# PERF_TYPE_RAW / CPU_CLK_UNHALTED.THREAD
[event18:base-stat]
fd=18
group_fd=11
type=4
config=34304
disabled=0
enable_on_exec=0
read_format=15
config=60
optional=1
# PERF_TYPE_RAW / topdown-mem-bound (0x8700)
# PERF_TYPE_RAW / INT_MISC.RECOVERY_CYCLES_ANY
[event19:base-stat]
fd=19
group_fd=11
type=4
config=34560
disabled=0
enable_on_exec=0
read_format=15
config=2097421
optional=1
# PERF_TYPE_RAW / CPU_CLK_UNHALTED.REF_XCLK
[event20:base-stat]
fd=20
type=4
config=316
optional=1
# PERF_TYPE_RAW / IDQ_UOPS_NOT_DELIVERED.CORE
[event21:base-stat]
fd=21
type=4
config=412
optional=1
# PERF_TYPE_RAW / CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE
[event22:base-stat]
fd=22
type=4
config=572
optional=1
# PERF_TYPE_RAW / UOPS_RETIRED.RETIRE_SLOTS
[event23:base-stat]
fd=23
type=4
config=706
optional=1
# PERF_TYPE_RAW / UOPS_ISSUED.ANY
[event24:base-stat]
fd=24
type=4
config=270
optional=1

111
tools/perf/tests/attr/test-stat-detailed-1
View File

@ -90,22 +90,11 @@ enable_on_exec=0
read_format=15
optional=1
# PERF_TYPE_RAW / topdown-bad-spec (0x8100)
# PERF_TYPE_RAW / topdown-fe-bound (0x8200)
[event13:base-stat]
fd=13
group_fd=11
type=4
config=33024
disabled=0
enable_on_exec=0
read_format=15
optional=1
# PERF_TYPE_RAW / topdown-fe-bound (0x8200)
[event14:base-stat]
fd=14
group_fd=11
type=4
config=33280
disabled=0
enable_on_exec=0
@ -113,8 +102,8 @@ read_format=15
optional=1
# PERF_TYPE_RAW / topdown-be-bound (0x8300)
[event15:base-stat]
fd=15
[event14:base-stat]
fd=14
group_fd=11
type=4
config=33536
@ -123,56 +112,86 @@ enable_on_exec=0
read_format=15
optional=1
# PERF_TYPE_RAW / topdown-heavy-ops (0x8400)
# PERF_TYPE_RAW / topdown-bad-spec (0x8100)
[event15:base-stat]
fd=15
group_fd=11
type=4
config=33024
disabled=0
enable_on_exec=0
read_format=15
optional=1
# PERF_TYPE_RAW / INT_MISC.UOP_DROPPING
[event16:base-stat]
fd=16
group_fd=11
type=4
config=33792
disabled=0
enable_on_exec=0
read_format=15
config=4109
optional=1
# PERF_TYPE_RAW / topdown-br-mispredict (0x8500)
# PERF_TYPE_RAW / cpu/INT_MISC.RECOVERY_CYCLES,cmask=1,edge/
[event17:base-stat]
fd=17
group_fd=11
type=4
config=34048
disabled=0
enable_on_exec=0
read_format=15
config=17039629
optional=1
# PERF_TYPE_RAW / topdown-fetch-lat (0x8600)
# PERF_TYPE_RAW / CPU_CLK_UNHALTED.THREAD
[event18:base-stat]
fd=18
group_fd=11
type=4
config=34304
disabled=0
enable_on_exec=0
read_format=15
config=60
optional=1
# PERF_TYPE_RAW / topdown-mem-bound (0x8700)
# PERF_TYPE_RAW / INT_MISC.RECOVERY_CYCLES_ANY
[event19:base-stat]
fd=19
group_fd=11
type=4
config=34560
disabled=0
enable_on_exec=0
read_format=15
config=2097421
optional=1
# PERF_TYPE_RAW / CPU_CLK_UNHALTED.REF_XCLK
[event20:base-stat]
fd=20
type=4
config=316
optional=1
# PERF_TYPE_RAW / IDQ_UOPS_NOT_DELIVERED.CORE
[event21:base-stat]
fd=21
type=4
config=412
optional=1
# PERF_TYPE_RAW / CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE
[event22:base-stat]
fd=22
type=4
config=572
optional=1
# PERF_TYPE_RAW / UOPS_RETIRED.RETIRE_SLOTS
[event23:base-stat]
fd=23
type=4
config=706
optional=1
# PERF_TYPE_RAW / UOPS_ISSUED.ANY
[event24:base-stat]
fd=24
type=4
config=270
optional=1
# PERF_TYPE_HW_CACHE /
# PERF_COUNT_HW_CACHE_L1D << 0 |
# (PERF_COUNT_HW_CACHE_OP_READ << 8) |
# (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)
[event20:base-stat]
fd=20
[event25:base-stat]
fd=25
type=3
config=0
optional=1
@ -181,8 +200,8 @@ optional=1
# PERF_COUNT_HW_CACHE_L1D << 0 |
# (PERF_COUNT_HW_CACHE_OP_READ << 8) |
# (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)
[event21:base-stat]
fd=21
[event26:base-stat]
fd=26
type=3
config=65536
optional=1
@ -191,8 +210,8 @@ optional=1
# PERF_COUNT_HW_CACHE_LL << 0 |
# (PERF_COUNT_HW_CACHE_OP_READ << 8) |
# (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)
[event22:base-stat]
fd=22
[event27:base-stat]
fd=27
type=3
config=2
optional=1
@ -201,8 +220,8 @@ optional=1
# PERF_COUNT_HW_CACHE_LL << 0 |
# (PERF_COUNT_HW_CACHE_OP_READ << 8) |
# (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)
[event23:base-stat]
fd=23
[event28:base-stat]
fd=28
type=3
config=65538
optional=1

135
tools/perf/tests/attr/test-stat-detailed-2
View File

@ -90,22 +90,11 @@ enable_on_exec=0
read_format=15
optional=1
# PERF_TYPE_RAW / topdown-bad-spec (0x8100)
# PERF_TYPE_RAW / topdown-fe-bound (0x8200)
[event13:base-stat]
fd=13
group_fd=11
type=4
config=33024
disabled=0
enable_on_exec=0
read_format=15
optional=1
# PERF_TYPE_RAW / topdown-fe-bound (0x8200)
[event14:base-stat]
fd=14
group_fd=11
type=4
config=33280
disabled=0
enable_on_exec=0
@ -113,8 +102,8 @@ read_format=15
optional=1
# PERF_TYPE_RAW / topdown-be-bound (0x8300)
[event15:base-stat]
fd=15
[event14:base-stat]
fd=14
group_fd=11
type=4
config=33536
@ -123,56 +112,86 @@ enable_on_exec=0
read_format=15
optional=1
# PERF_TYPE_RAW / topdown-heavy-ops (0x8400)
# PERF_TYPE_RAW / topdown-bad-spec (0x8100)
[event15:base-stat]
fd=15
group_fd=11
type=4
config=33024
disabled=0
enable_on_exec=0
read_format=15
optional=1
# PERF_TYPE_RAW / INT_MISC.UOP_DROPPING
[event16:base-stat]
fd=16
group_fd=11
type=4
config=33792
disabled=0
enable_on_exec=0
read_format=15
config=4109
optional=1
# PERF_TYPE_RAW / topdown-br-mispredict (0x8500)
# PERF_TYPE_RAW / cpu/INT_MISC.RECOVERY_CYCLES,cmask=1,edge/
[event17:base-stat]
fd=17
group_fd=11
type=4
config=34048
disabled=0
enable_on_exec=0
read_format=15
config=17039629
optional=1
# PERF_TYPE_RAW / topdown-fetch-lat (0x8600)
# PERF_TYPE_RAW / CPU_CLK_UNHALTED.THREAD
[event18:base-stat]
fd=18
group_fd=11
type=4
config=34304
disabled=0
enable_on_exec=0
read_format=15
config=60
optional=1
# PERF_TYPE_RAW / topdown-mem-bound (0x8700)
# PERF_TYPE_RAW / INT_MISC.RECOVERY_CYCLES_ANY
[event19:base-stat]
fd=19
group_fd=11
type=4
config=34560
disabled=0
enable_on_exec=0
read_format=15
config=2097421
optional=1
# PERF_TYPE_RAW / CPU_CLK_UNHALTED.REF_XCLK
[event20:base-stat]
fd=20
type=4
config=316
optional=1
# PERF_TYPE_RAW / IDQ_UOPS_NOT_DELIVERED.CORE
[event21:base-stat]
fd=21
type=4
config=412
optional=1
# PERF_TYPE_RAW / CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE
[event22:base-stat]
fd=22
type=4
config=572
optional=1
# PERF_TYPE_RAW / UOPS_RETIRED.RETIRE_SLOTS
[event23:base-stat]
fd=23
type=4
config=706
optional=1
# PERF_TYPE_RAW / UOPS_ISSUED.ANY
[event24:base-stat]
fd=24
type=4
config=270
optional=1
# PERF_TYPE_HW_CACHE /
# PERF_COUNT_HW_CACHE_L1D << 0 |
# (PERF_COUNT_HW_CACHE_OP_READ << 8) |
# (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)
[event20:base-stat]
fd=20
[event25:base-stat]
fd=25
type=3
config=0
optional=1
@ -181,8 +200,8 @@ optional=1
# PERF_COUNT_HW_CACHE_L1D << 0 |
# (PERF_COUNT_HW_CACHE_OP_READ << 8) |
# (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)
[event21:base-stat]
fd=21
[event26:base-stat]
fd=26
type=3
config=65536
optional=1
@ -191,8 +210,8 @@ optional=1
# PERF_COUNT_HW_CACHE_LL << 0 |
# (PERF_COUNT_HW_CACHE_OP_READ << 8) |
# (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)
[event22:base-stat]
fd=22
[event27:base-stat]
fd=27
type=3
config=2
optional=1
@ -201,8 +220,8 @@ optional=1
# PERF_COUNT_HW_CACHE_LL << 0 |
# (PERF_COUNT_HW_CACHE_OP_READ << 8) |
# (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)
[event23:base-stat]
fd=23
[event28:base-stat]
fd=28
type=3
config=65538
optional=1
@ -211,8 +230,8 @@ optional=1
# PERF_COUNT_HW_CACHE_L1I << 0 |
# (PERF_COUNT_HW_CACHE_OP_READ << 8) |
# (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)
[event24:base-stat]
fd=24
[event29:base-stat]
fd=29
type=3
config=1
optional=1
@ -221,8 +240,8 @@ optional=1
# PERF_COUNT_HW_CACHE_L1I << 0 |
# (PERF_COUNT_HW_CACHE_OP_READ << 8) |
# (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)
[event25:base-stat]
fd=25
[event30:base-stat]
fd=30
type=3
config=65537
optional=1
@ -231,8 +250,8 @@ optional=1
# PERF_COUNT_HW_CACHE_DTLB << 0 |
# (PERF_COUNT_HW_CACHE_OP_READ << 8) |
# (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)
[event26:base-stat]
fd=26
[event31:base-stat]
fd=31
type=3
config=3
optional=1
@ -241,8 +260,8 @@ optional=1
# PERF_COUNT_HW_CACHE_DTLB << 0 |
# (PERF_COUNT_HW_CACHE_OP_READ << 8) |
# (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)
[event27:base-stat]
fd=27
[event32:base-stat]
fd=32
type=3
config=65539
optional=1
@ -251,8 +270,8 @@ optional=1
# PERF_COUNT_HW_CACHE_ITLB << 0 |
# (PERF_COUNT_HW_CACHE_OP_READ << 8) |
# (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)
[event28:base-stat]
fd=28
[event33:base-stat]
fd=33
type=3
config=4
optional=1
@ -261,8 +280,8 @@ optional=1
# PERF_COUNT_HW_CACHE_ITLB << 0 |
# (PERF_COUNT_HW_CACHE_OP_READ << 8) |
# (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)
[event29:base-stat]
fd=29
[event34:base-stat]
fd=34
type=3
config=65540
optional=1

143
tools/perf/tests/attr/test-stat-detailed-3
View File

@ -90,22 +90,11 @@ enable_on_exec=0
read_format=15
optional=1
# PERF_TYPE_RAW / topdown-bad-spec (0x8100)
# PERF_TYPE_RAW / topdown-fe-bound (0x8200)
[event13:base-stat]
fd=13
group_fd=11
type=4
config=33024
disabled=0
enable_on_exec=0
read_format=15
optional=1
# PERF_TYPE_RAW / topdown-fe-bound (0x8200)
[event14:base-stat]
fd=14
group_fd=11
type=4
config=33280
disabled=0
enable_on_exec=0
@ -113,8 +102,8 @@ read_format=15
optional=1
# PERF_TYPE_RAW / topdown-be-bound (0x8300)
[event15:base-stat]
fd=15
[event14:base-stat]
fd=14
group_fd=11
type=4
config=33536
@ -123,56 +112,86 @@ enable_on_exec=0
read_format=15
optional=1
# PERF_TYPE_RAW / topdown-heavy-ops (0x8400)
# PERF_TYPE_RAW / topdown-bad-spec (0x8100)
[event15:base-stat]
fd=15
group_fd=11
type=4
config=33024
disabled=0
enable_on_exec=0
read_format=15
optional=1
# PERF_TYPE_RAW / INT_MISC.UOP_DROPPING
[event16:base-stat]
fd=16
group_fd=11
type=4
config=33792
disabled=0
enable_on_exec=0
read_format=15
config=4109
optional=1
# PERF_TYPE_RAW / topdown-br-mispredict (0x8500)
# PERF_TYPE_RAW / cpu/INT_MISC.RECOVERY_CYCLES,cmask=1,edge/
[event17:base-stat]
fd=17
group_fd=11
type=4
config=34048
disabled=0
enable_on_exec=0
read_format=15
config=17039629
optional=1
# PERF_TYPE_RAW / topdown-fetch-lat (0x8600)
# PERF_TYPE_RAW / CPU_CLK_UNHALTED.THREAD
[event18:base-stat]
fd=18
group_fd=11
type=4
config=34304
disabled=0
enable_on_exec=0
read_format=15
config=60
optional=1
# PERF_TYPE_RAW / topdown-mem-bound (0x8700)
# PERF_TYPE_RAW / INT_MISC.RECOVERY_CYCLES_ANY
[event19:base-stat]
fd=19
group_fd=11
type=4
config=34560
disabled=0
enable_on_exec=0
read_format=15
config=2097421
optional=1
# PERF_TYPE_RAW / CPU_CLK_UNHALTED.REF_XCLK
[event20:base-stat]
fd=20
type=4
config=316
optional=1
# PERF_TYPE_RAW / IDQ_UOPS_NOT_DELIVERED.CORE
[event21:base-stat]
fd=21
type=4
config=412
optional=1
# PERF_TYPE_RAW / CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE
[event22:base-stat]
fd=22
type=4
config=572
optional=1
# PERF_TYPE_RAW / UOPS_RETIRED.RETIRE_SLOTS
[event23:base-stat]
fd=23
type=4
config=706
optional=1
# PERF_TYPE_RAW / UOPS_ISSUED.ANY
[event24:base-stat]
fd=24
type=4
config=270
optional=1
# PERF_TYPE_HW_CACHE /
# PERF_COUNT_HW_CACHE_L1D << 0 |
# (PERF_COUNT_HW_CACHE_OP_READ << 8) |
# (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)
[event20:base-stat]
fd=20
[event25:base-stat]
fd=25
type=3
config=0
optional=1
@ -181,8 +200,8 @@ optional=1
# PERF_COUNT_HW_CACHE_L1D << 0 |
# (PERF_COUNT_HW_CACHE_OP_READ << 8) |
# (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)
[event21:base-stat]
fd=21
[event26:base-stat]
fd=26
type=3
config=65536
optional=1
@ -191,8 +210,8 @@ optional=1
# PERF_COUNT_HW_CACHE_LL << 0 |
# (PERF_COUNT_HW_CACHE_OP_READ << 8) |
# (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)
[event22:base-stat]
fd=22
[event27:base-stat]
fd=27
type=3
config=2
optional=1
@ -201,8 +220,8 @@ optional=1
# PERF_COUNT_HW_CACHE_LL << 0 |
# (PERF_COUNT_HW_CACHE_OP_READ << 8) |
# (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)
[event23:base-stat]
fd=23
[event28:base-stat]
fd=28
type=3
config=65538
optional=1
@ -211,8 +230,8 @@ optional=1
# PERF_COUNT_HW_CACHE_L1I << 0 |
# (PERF_COUNT_HW_CACHE_OP_READ << 8) |
# (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)
[event24:base-stat]
fd=24
[event29:base-stat]
fd=29
type=3
config=1
optional=1
@ -221,8 +240,8 @@ optional=1
# PERF_COUNT_HW_CACHE_L1I << 0 |
# (PERF_COUNT_HW_CACHE_OP_READ << 8) |
# (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)
[event25:base-stat]
fd=25
[event30:base-stat]
fd=30
type=3
config=65537
optional=1
@ -231,8 +250,8 @@ optional=1
# PERF_COUNT_HW_CACHE_DTLB << 0 |
# (PERF_COUNT_HW_CACHE_OP_READ << 8) |
# (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)
[event26:base-stat]
fd=26
[event31:base-stat]
fd=31
type=3
config=3
optional=1
@ -241,8 +260,8 @@ optional=1
# PERF_COUNT_HW_CACHE_DTLB << 0 |
# (PERF_COUNT_HW_CACHE_OP_READ << 8) |
# (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)
[event27:base-stat]
fd=27
[event32:base-stat]
fd=32
type=3
config=65539
optional=1
@ -251,8 +270,8 @@ optional=1
# PERF_COUNT_HW_CACHE_ITLB << 0 |
# (PERF_COUNT_HW_CACHE_OP_READ << 8) |
# (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)
[event28:base-stat]
fd=28
[event33:base-stat]
fd=33
type=3
config=4
optional=1
@ -261,8 +280,8 @@ optional=1
# PERF_COUNT_HW_CACHE_ITLB << 0 |
# (PERF_COUNT_HW_CACHE_OP_READ << 8) |
# (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)
[event29:base-stat]
fd=29
[event34:base-stat]
fd=34
type=3
config=65540
optional=1
@ -271,8 +290,8 @@ optional=1
# PERF_COUNT_HW_CACHE_L1D << 0 |
# (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) |
# (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)
[event30:base-stat]
fd=30
[event35:base-stat]
fd=35
type=3
config=512
optional=1
@ -281,8 +300,8 @@ optional=1
# PERF_COUNT_HW_CACHE_L1D << 0 |
# (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) |
# (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)
[event31:base-stat]
fd=31
[event36:base-stat]
fd=36
type=3
config=66048
optional=1

2
tools/perf/trace/beauty/arch_prctl.c
View File

@ -12,10 +12,12 @@
static DEFINE_STRARRAY_OFFSET(x86_arch_prctl_codes_1, "ARCH_", x86_arch_prctl_codes_1_offset);
static DEFINE_STRARRAY_OFFSET(x86_arch_prctl_codes_2, "ARCH_", x86_arch_prctl_codes_2_offset);
static DEFINE_STRARRAY_OFFSET(x86_arch_prctl_codes_3, "ARCH_", x86_arch_prctl_codes_3_offset);
static struct strarray *x86_arch_prctl_codes[] = {
&strarray__x86_arch_prctl_codes_1,
&strarray__x86_arch_prctl_codes_2,
&strarray__x86_arch_prctl_codes_3,
};
static DEFINE_STRARRAYS(x86_arch_prctl_codes);

1
tools/perf/trace/beauty/x86_arch_prctl.sh
View File

@ -24,3 +24,4 @@ print_range () {
print_range 1 0x1 0x1001
print_range 2 0x2 0x2001
print_range 3 0x4 0x4001

2
tools/perf/util/metricgroup.c
View File

@ -1719,7 +1719,7 @@ static int metricgroup__topdown_max_level_callback(const struct pmu_metric *pm,
{
unsigned int *max_level = data;
unsigned int level;
const char *p = strstr(pm->metric_group, "TopdownL");
const char *p = strstr(pm->metric_group ?: "", "TopdownL");
if (!p || p[8] == '\0')
return 0;