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drm/amdgpu: PWRBRK sequence changes for Aldebaran 

Modify power brake enablement sequence on Aldebaran

Signed-off-by: Ashish Pawar <ashish.pawar@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Ashish Pawar 2021-06-17 13:51:23 +08:00 committed by Alex Deucher
parent 6ec598cc9d
commit 7c5f3d7d61
1 changed files with 0 additions and 5 deletions
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5
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
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@ -782,11 +782,6 @@ void gfx_v9_4_2_set_power_brake_sequence(struct amdgpu_device *adev)
tmp = REG_SET_FIELD(tmp, GC_THROTTLE_CTRL1, PWRBRK_STALL_EN, 1);
WREG32_SOC15(GC, 0, regGC_THROTTLE_CTRL1, tmp);
WREG32_SOC15(GC, 0, regDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);
tmp = 0;
tmp = REG_SET_FIELD(tmp, DIDT_SQ_THROTTLE_CTRL, PWRBRK_STALL_EN, 1);
WREG32_SOC15(GC, 0, regDIDT_IND_DATA, tmp);
WREG32_SOC15(GC, 0, regGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
tmp = 0;
tmp = REG_SET_FIELD(tmp, PWRBRK_STALL_PATTERN_CTRL, PWRBRK_END_STEP, 0x12);