drm/amd/display: Add DCN3 chip ids
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -166,6 +166,7 @@ enum {
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NV_NAVI10_P_A0 = 1,
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NV_NAVI12_P_A0 = 10,
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NV_NAVI14_M_A0 = 20,
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NV_SIENNA_CICHLID_P_A0 = 40,
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NV_UNKNOWN = 0xFF
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};
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@ -173,6 +174,9 @@ enum {
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#define ASICREV_IS_NAVI12_P(eChipRev) ((eChipRev >= NV_NAVI12_P_A0) && (eChipRev < NV_NAVI14_M_A0))
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#define ASICREV_IS_NAVI14_M(eChipRev) ((eChipRev >= NV_NAVI14_M_A0) && (eChipRev < NV_UNKNOWN))
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#define ASICREV_IS_RENOIR(eChipRev) ((eChipRev >= RENOIR_A0) && (eChipRev < RAVEN1_F0))
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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#define ASICREV_IS_SIENNA_CICHLID_P(eChipRev) ((eChipRev >= NV_SIENNA_CICHLID_P_A0))
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#endif
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/*
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* ASIC chip ID
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@ -48,6 +48,7 @@ enum dce_version {
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DCN_VERSION_1_01,
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DCN_VERSION_2_0,
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DCN_VERSION_2_1,
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DCN_VERSION_3_0,
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DCN_VERSION_MAX
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};
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