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[media] marvell-ccic: reset ccic phy when stop streaming for stability 

This patch adds the reset ccic phy operation when stop streaming.
Stop streaming without reset ccic phy, the next start streaming
may be unstable.
Also need add CCIC2 definition when PXA688/PXA2128 support dual ccics.

Signed-off-by: Albert Wang <twang13@marvell.com>
Signed-off-by: Libin Yang <lbyang@marvell.com>
Acked-by: Jonathan Corbet <corbet@lwn.net>
Acked-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
This commit is contained in:
Libin Yang 2013-07-03 01:56:00 -03:00 committed by Mauro Carvalho Chehab
parent 0e394f44fb
commit 7c269f454e
3 changed files with 33 additions and 0 deletions
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6
drivers/media/platform/marvell-ccic/mcam-core.c
View File

@ -1040,6 +1040,12 @@ static int mcam_vb_stop_streaming(struct vb2_queue *vq)
if (cam->state != S_STREAMING)
return -EINVAL;
mcam_ctlr_stop_dma(cam);
/*
* Reset the CCIC PHY after stopping streaming,
* otherwise, the CCIC may be unstable.
*/
if (cam->ctlr_reset)
cam->ctlr_reset(cam);
/*
* VB2 reclaims the buffers, so we need to forget
* about them.

2
drivers/media/platform/marvell-ccic/mcam-core.h
View File

@ -115,6 +115,7 @@ struct mcam_camera {
int mclk_src; /* which clock source the mclk derives from */
int mclk_div; /* Clock Divider Value for MCLK */
int ccic_id;
enum v4l2_mbus_type bus_type;
/* MIPI support */
/* The dphy config value, allocated in board file
@ -135,6 +136,7 @@ struct mcam_camera {
int (*plat_power_up) (struct mcam_camera *cam);
void (*plat_power_down) (struct mcam_camera *cam);
void (*calc_dphy) (struct mcam_camera *cam);
void (*ctlr_reset) (struct mcam_camera *cam);
/*
* Everything below here is private to the mcam core and

25
drivers/media/platform/marvell-ccic/mmp-driver.c
View File

@ -105,6 +105,7 @@ static struct mmp_camera *mmpcam_find_device(struct platform_device *pdev)
#define CPU_SUBSYS_PMU_BASE 0xd4282800
#define REG_CCIC_DCGCR 0x28 /* CCIC dyn clock gate ctrl reg */
#define REG_CCIC_CRCR 0x50 /* CCIC clk reset ctrl reg */
#define REG_CCIC2_CRCR 0xf4 /* CCIC2 clk reset ctrl reg */
static void mcam_clk_enable(struct mcam_camera *mcam)
{
@ -194,6 +195,28 @@ static void mmpcam_power_down(struct mcam_camera *mcam)
mcam_clk_disable(mcam);
}
void mcam_ctlr_reset(struct mcam_camera *mcam)
{
unsigned long val;
struct mmp_camera *cam = mcam_to_cam(mcam);
if (mcam->ccic_id) {
/*
* Using CCIC2
*/
val = ioread32(cam->power_regs + REG_CCIC2_CRCR);
iowrite32(val & ~0x2, cam->power_regs + REG_CCIC2_CRCR);
iowrite32(val | 0x2, cam->power_regs + REG_CCIC2_CRCR);
} else {
/*
* Using CCIC1
*/
val = ioread32(cam->power_regs + REG_CCIC_CRCR);
iowrite32(val & ~0x2, cam->power_regs + REG_CCIC_CRCR);
iowrite32(val | 0x2, cam->power_regs + REG_CCIC_CRCR);
}
}
/*
* calc the dphy register values
* There are three dphy registers being used.
@ -354,9 +377,11 @@ static int mmpcam_probe(struct platform_device *pdev)
mcam = &cam->mcam;
mcam->plat_power_up = mmpcam_power_up;
mcam->plat_power_down = mmpcam_power_down;
mcam->ctlr_reset = mcam_ctlr_reset;
mcam->calc_dphy = mmpcam_calc_dphy;
mcam->dev = &pdev->dev;
mcam->use_smbus = 0;
mcam->ccic_id = pdev->id;
mcam->mclk_min = pdata->mclk_min;
mcam->mclk_src = pdata->mclk_src;
mcam->mclk_div = pdata->mclk_div;