drm/amd/pm: enable BACO support for SMU 13.0.0
Enable SMU 13.0.0 BACO support. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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06845732df
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@ -282,5 +282,16 @@ int smu_v13_0_deep_sleep_control(struct smu_context *smu,
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int smu_v13_0_gfx_ulv_control(struct smu_context *smu,
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bool enablement);
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bool smu_v13_0_baco_is_support(struct smu_context *smu);
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enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu);
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int smu_v13_0_baco_set_state(struct smu_context *smu,
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enum smu_baco_state state);
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int smu_v13_0_baco_enter(struct smu_context *smu);
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int smu_v13_0_baco_exit(struct smu_context *smu);
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#endif
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#endif
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@ -2206,3 +2206,78 @@ int smu_v13_0_gfx_ulv_control(struct smu_context *smu,
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return ret;
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}
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bool smu_v13_0_baco_is_support(struct smu_context *smu)
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{
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struct smu_baco_context *smu_baco = &smu->smu_baco;
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if (amdgpu_sriov_vf(smu->adev) ||
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!smu_baco->platform_support)
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return false;
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if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
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!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
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return false;
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return true;
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}
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enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu)
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{
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struct smu_baco_context *smu_baco = &smu->smu_baco;
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return smu_baco->state;
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}
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int smu_v13_0_baco_set_state(struct smu_context *smu,
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enum smu_baco_state state)
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{
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struct smu_baco_context *smu_baco = &smu->smu_baco;
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struct amdgpu_device *adev = smu->adev;
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int ret = 0;
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if (smu_v13_0_baco_get_state(smu) == state)
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return 0;
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if (state == SMU_BACO_STATE_ENTER) {
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ret = smu_cmn_send_smc_msg_with_param(smu,
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SMU_MSG_EnterBaco,
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0,
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NULL);
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} else {
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ret = smu_cmn_send_smc_msg(smu,
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SMU_MSG_ExitBaco,
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NULL);
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if (ret)
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return ret;
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/* clear vbios scratch 6 and 7 for coming asic reinit */
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WREG32(adev->bios_scratch_reg_offset + 6, 0);
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WREG32(adev->bios_scratch_reg_offset + 7, 0);
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}
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if (!ret)
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smu_baco->state = state;
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return ret;
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}
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int smu_v13_0_baco_enter(struct smu_context *smu)
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{
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int ret = 0;
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ret = smu_v13_0_baco_set_state(smu,
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SMU_BACO_STATE_ENTER);
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if (ret)
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return ret;
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msleep(10);
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return ret;
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}
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int smu_v13_0_baco_exit(struct smu_context *smu)
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{
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return smu_v13_0_baco_set_state(smu,
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SMU_BACO_STATE_EXIT);
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}
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@ -95,6 +95,7 @@ static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] =
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MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
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MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
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MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
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MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
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MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1),
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MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
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MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1),
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@ -150,6 +151,7 @@ static struct cmn2asic_mapping smu_v13_0_0_feature_mask_map[SMU_FEATURE_COUNT] =
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[SMU_FEATURE_DS_MP0CLK_BIT] = {1, FEATURE_SOC_MPCLK_DS_BIT},
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[SMU_FEATURE_DS_MP1CLK_BIT] = {1, FEATURE_BACO_MPCLK_DS_BIT},
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[SMU_FEATURE_GFX_ULV_BIT] = {1, FEATURE_GFX_ULV_BIT},
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[SMU_FEATURE_BACO_BIT] = {1, FEATURE_BACO_BIT},
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};
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static struct cmn2asic_mapping smu_v13_0_0_table_map[SMU_TABLE_COUNT] = {
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@ -1595,6 +1597,11 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
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.set_tool_table_location = smu_v13_0_set_tool_table_location,
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.deep_sleep_control = smu_v13_0_deep_sleep_control,
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.gfx_ulv_control = smu_v13_0_gfx_ulv_control,
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.baco_is_support = smu_v13_0_baco_is_support,
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.baco_get_state = smu_v13_0_baco_get_state,
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.baco_set_state = smu_v13_0_baco_set_state,
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.baco_enter = smu_v13_0_baco_enter,
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.baco_exit = smu_v13_0_baco_exit,
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};
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void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu)
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