iop-adma: P+Q support for iop13xx adma engines
iop33x support is not included because that engine is a bit more awkward
to handle in that it can either be in xor mode or pq mode. The
dmaengine/async_tx layers currently only comprehend static capabilities.
Note iop13xx does not support hardware PQ continuation so the driver
must handle the DMA_PREP_CONTINUE flag for operations across > 16
sources. From the comment for dma_maxpq:
/* When an engine does not support native continuation we need 3 extra
* source slots to reuse P and Q with the following coefficients:
* 1/ {00} * P : remove P from Q', but use it as a source for P'
* 2/ {01} * Q : use Q to continue Q' calculation
* 3/ {00} * Q : subtract Q from P' to cancel (2)
*/
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
Dan Williams
parent
72be12f0c3
commit
7bf649aee8
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@ -187,11 +187,74 @@ union iop3xx_desc {
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void *ptr;
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};
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/* No support for p+q operations */
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static inline int
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iop_chan_pq_slot_count(size_t len, int src_cnt, int *slots_per_op)
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{
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BUG();
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return 0;
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}
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static inline void
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iop_desc_init_pq(struct iop_adma_desc_slot *desc, int src_cnt,
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unsigned long flags)
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{
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BUG();
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}
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static inline void
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iop_desc_set_pq_addr(struct iop_adma_desc_slot *desc, dma_addr_t *addr)
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{
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BUG();
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}
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static inline void
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iop_desc_set_pq_src_addr(struct iop_adma_desc_slot *desc, int src_idx,
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dma_addr_t addr, unsigned char coef)
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{
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BUG();
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}
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static inline int
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iop_chan_pq_zero_sum_slot_count(size_t len, int src_cnt, int *slots_per_op)
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{
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BUG();
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return 0;
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}
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static inline void
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iop_desc_init_pq_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt,
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unsigned long flags)
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{
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BUG();
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}
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static inline void
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iop_desc_set_pq_zero_sum_byte_count(struct iop_adma_desc_slot *desc, u32 len)
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{
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BUG();
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}
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#define iop_desc_set_pq_zero_sum_src_addr iop_desc_set_pq_src_addr
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static inline void
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iop_desc_set_pq_zero_sum_addr(struct iop_adma_desc_slot *desc, int pq_idx,
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dma_addr_t *src)
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{
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BUG();
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}
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static inline int iop_adma_get_max_xor(void)
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{
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return 32;
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}
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static inline int iop_adma_get_max_pq(void)
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{
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BUG();
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return 0;
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}
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static inline u32 iop_chan_get_current_descriptor(struct iop_adma_chan *chan)
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{
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int id = chan->device->id;
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@ -332,6 +395,11 @@ static inline int iop_chan_zero_sum_slot_count(size_t len, int src_cnt,
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return slot_cnt;
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}
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static inline int iop_desc_is_pq(struct iop_adma_desc_slot *desc)
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{
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return 0;
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}
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static inline u32 iop_desc_get_dest_addr(struct iop_adma_desc_slot *desc,
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struct iop_adma_chan *chan)
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{
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@ -349,6 +417,14 @@ static inline u32 iop_desc_get_dest_addr(struct iop_adma_desc_slot *desc,
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return 0;
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}
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static inline u32 iop_desc_get_qdest_addr(struct iop_adma_desc_slot *desc,
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struct iop_adma_chan *chan)
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{
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BUG();
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return 0;
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}
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static inline u32 iop_desc_get_byte_count(struct iop_adma_desc_slot *desc,
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struct iop_adma_chan *chan)
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{
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@ -106,6 +106,7 @@ struct iop_adma_desc_slot {
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union {
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u32 *xor_check_result;
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u32 *crc32_result;
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u32 *pq_check_result;
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};
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};
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@ -150,6 +150,8 @@ static inline int iop_adma_get_max_xor(void)
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return 16;
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}
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#define iop_adma_get_max_pq iop_adma_get_max_xor
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static inline u32 iop_chan_get_current_descriptor(struct iop_adma_chan *chan)
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{
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return __raw_readl(ADMA_ADAR(chan));
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@ -211,7 +213,10 @@ iop_chan_xor_slot_count(size_t len, int src_cnt, int *slots_per_op)
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#define IOP_ADMA_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
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#define IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
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#define IOP_ADMA_XOR_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
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#define IOP_ADMA_PQ_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
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#define iop_chan_zero_sum_slot_count(l, s, o) iop_chan_xor_slot_count(l, s, o)
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#define iop_chan_pq_slot_count iop_chan_xor_slot_count
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#define iop_chan_pq_zero_sum_slot_count iop_chan_xor_slot_count
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static inline u32 iop_desc_get_dest_addr(struct iop_adma_desc_slot *desc,
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struct iop_adma_chan *chan)
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@ -220,6 +225,13 @@ static inline u32 iop_desc_get_dest_addr(struct iop_adma_desc_slot *desc,
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return hw_desc->dest_addr;
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}
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static inline u32 iop_desc_get_qdest_addr(struct iop_adma_desc_slot *desc,
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struct iop_adma_chan *chan)
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{
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struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
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return hw_desc->q_dest_addr;
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}
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static inline u32 iop_desc_get_byte_count(struct iop_adma_desc_slot *desc,
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struct iop_adma_chan *chan)
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{
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@ -319,6 +331,58 @@ iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt,
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return 1;
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}
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static inline void
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iop_desc_init_pq(struct iop_adma_desc_slot *desc, int src_cnt,
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unsigned long flags)
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{
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struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
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union {
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u32 value;
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struct iop13xx_adma_desc_ctrl field;
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} u_desc_ctrl;
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u_desc_ctrl.value = 0;
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u_desc_ctrl.field.src_select = src_cnt - 1;
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u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
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u_desc_ctrl.field.pq_xfer_en = 1;
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u_desc_ctrl.field.p_xfer_dis = !!(flags & DMA_PREP_PQ_DISABLE_P);
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u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
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hw_desc->desc_ctrl = u_desc_ctrl.value;
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}
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static inline int iop_desc_is_pq(struct iop_adma_desc_slot *desc)
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{
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struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
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union {
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u32 value;
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struct iop13xx_adma_desc_ctrl field;
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} u_desc_ctrl;
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u_desc_ctrl.value = hw_desc->desc_ctrl;
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return u_desc_ctrl.field.pq_xfer_en;
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}
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static inline void
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iop_desc_init_pq_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt,
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unsigned long flags)
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{
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struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
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union {
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u32 value;
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struct iop13xx_adma_desc_ctrl field;
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} u_desc_ctrl;
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u_desc_ctrl.value = 0;
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u_desc_ctrl.field.src_select = src_cnt - 1;
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u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
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u_desc_ctrl.field.zero_result = 1;
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u_desc_ctrl.field.status_write_back_en = 1;
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u_desc_ctrl.field.pq_xfer_en = 1;
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u_desc_ctrl.field.p_xfer_dis = !!(flags & DMA_PREP_PQ_DISABLE_P);
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u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
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hw_desc->desc_ctrl = u_desc_ctrl.value;
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}
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static inline void iop_desc_set_byte_count(struct iop_adma_desc_slot *desc,
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struct iop_adma_chan *chan,
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u32 byte_count)
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@ -351,6 +415,7 @@ iop_desc_set_zero_sum_byte_count(struct iop_adma_desc_slot *desc, u32 len)
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}
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}
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#define iop_desc_set_pq_zero_sum_byte_count iop_desc_set_zero_sum_byte_count
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static inline void iop_desc_set_dest_addr(struct iop_adma_desc_slot *desc,
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struct iop_adma_chan *chan,
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@ -361,6 +426,16 @@ static inline void iop_desc_set_dest_addr(struct iop_adma_desc_slot *desc,
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hw_desc->upper_dest_addr = 0;
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}
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static inline void
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iop_desc_set_pq_addr(struct iop_adma_desc_slot *desc, dma_addr_t *addr)
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{
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struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
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hw_desc->dest_addr = addr[0];
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hw_desc->q_dest_addr = addr[1];
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hw_desc->upper_dest_addr = 0;
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}
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static inline void iop_desc_set_memcpy_src_addr(struct iop_adma_desc_slot *desc,
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dma_addr_t addr)
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{
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@ -388,6 +463,29 @@ static inline void iop_desc_set_xor_src_addr(struct iop_adma_desc_slot *desc,
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} while (slot_cnt);
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}
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static inline void
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iop_desc_set_pq_src_addr(struct iop_adma_desc_slot *desc, int src_idx,
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dma_addr_t addr, unsigned char coef)
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{
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int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op;
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struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc, *iter;
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struct iop13xx_adma_src *src;
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int i = 0;
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do {
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iter = iop_hw_desc_slot_idx(hw_desc, i);
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src = &iter->src[src_idx];
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src->src_addr = addr;
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src->pq_upper_src_addr = 0;
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src->pq_dmlt = coef;
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slot_cnt -= slots_per_op;
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if (slot_cnt) {
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i += slots_per_op;
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addr += IOP_ADMA_PQ_MAX_BYTE_COUNT;
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}
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} while (slot_cnt);
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}
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static inline void
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iop_desc_init_interrupt(struct iop_adma_desc_slot *desc,
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struct iop_adma_chan *chan)
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@ -399,6 +497,15 @@ iop_desc_init_interrupt(struct iop_adma_desc_slot *desc,
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}
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#define iop_desc_set_zero_sum_src_addr iop_desc_set_xor_src_addr
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#define iop_desc_set_pq_zero_sum_src_addr iop_desc_set_pq_src_addr
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static inline void
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iop_desc_set_pq_zero_sum_addr(struct iop_adma_desc_slot *desc, int pq_idx,
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dma_addr_t *src)
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{
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iop_desc_set_xor_src_addr(desc, pq_idx, src[pq_idx]);
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iop_desc_set_xor_src_addr(desc, pq_idx+1, src[pq_idx+1]);
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}
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static inline void iop_desc_set_next_desc(struct iop_adma_desc_slot *desc,
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u32 next_desc_addr)
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@ -57,6 +57,80 @@ static void iop_adma_free_slots(struct iop_adma_desc_slot *slot)
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}
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}
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static void
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iop_desc_unmap(struct iop_adma_chan *iop_chan, struct iop_adma_desc_slot *desc)
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{
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struct dma_async_tx_descriptor *tx = &desc->async_tx;
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struct iop_adma_desc_slot *unmap = desc->group_head;
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struct device *dev = &iop_chan->device->pdev->dev;
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u32 len = unmap->unmap_len;
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enum dma_ctrl_flags flags = tx->flags;
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u32 src_cnt;
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dma_addr_t addr;
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dma_addr_t dest;
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src_cnt = unmap->unmap_src_cnt;
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dest = iop_desc_get_dest_addr(unmap, iop_chan);
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if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
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enum dma_data_direction dir;
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if (src_cnt > 1) /* is xor? */
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dir = DMA_BIDIRECTIONAL;
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else
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dir = DMA_FROM_DEVICE;
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dma_unmap_page(dev, dest, len, dir);
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}
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if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
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while (src_cnt--) {
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addr = iop_desc_get_src_addr(unmap, iop_chan, src_cnt);
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if (addr == dest)
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continue;
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dma_unmap_page(dev, addr, len, DMA_TO_DEVICE);
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}
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}
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desc->group_head = NULL;
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}
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static void
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iop_desc_unmap_pq(struct iop_adma_chan *iop_chan, struct iop_adma_desc_slot *desc)
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{
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struct dma_async_tx_descriptor *tx = &desc->async_tx;
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struct iop_adma_desc_slot *unmap = desc->group_head;
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struct device *dev = &iop_chan->device->pdev->dev;
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u32 len = unmap->unmap_len;
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enum dma_ctrl_flags flags = tx->flags;
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u32 src_cnt = unmap->unmap_src_cnt;
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dma_addr_t pdest = iop_desc_get_dest_addr(unmap, iop_chan);
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dma_addr_t qdest = iop_desc_get_qdest_addr(unmap, iop_chan);
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int i;
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if (tx->flags & DMA_PREP_CONTINUE)
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src_cnt -= 3;
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if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP) && !desc->pq_check_result) {
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dma_unmap_page(dev, pdest, len, DMA_BIDIRECTIONAL);
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dma_unmap_page(dev, qdest, len, DMA_BIDIRECTIONAL);
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}
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if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
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dma_addr_t addr;
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for (i = 0; i < src_cnt; i++) {
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addr = iop_desc_get_src_addr(unmap, iop_chan, i);
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dma_unmap_page(dev, addr, len, DMA_TO_DEVICE);
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}
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if (desc->pq_check_result) {
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dma_unmap_page(dev, pdest, len, DMA_TO_DEVICE);
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dma_unmap_page(dev, qdest, len, DMA_TO_DEVICE);
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}
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}
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desc->group_head = NULL;
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}
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static dma_cookie_t
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iop_adma_run_tx_complete_actions(struct iop_adma_desc_slot *desc,
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struct iop_adma_chan *iop_chan, dma_cookie_t cookie)
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@ -78,40 +152,10 @@ iop_adma_run_tx_complete_actions(struct iop_adma_desc_slot *desc,
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* (unmap_single vs unmap_page?)
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*/
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if (desc->group_head && desc->unmap_len) {
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struct iop_adma_desc_slot *unmap = desc->group_head;
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struct device *dev =
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&iop_chan->device->pdev->dev;
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u32 len = unmap->unmap_len;
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enum dma_ctrl_flags flags = tx->flags;
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u32 src_cnt;
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dma_addr_t addr;
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dma_addr_t dest;
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src_cnt = unmap->unmap_src_cnt;
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dest = iop_desc_get_dest_addr(unmap, iop_chan);
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if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
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enum dma_data_direction dir;
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if (src_cnt > 1) /* is xor? */
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dir = DMA_BIDIRECTIONAL;
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else
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dir = DMA_FROM_DEVICE;
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dma_unmap_page(dev, dest, len, dir);
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}
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if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
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while (src_cnt--) {
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addr = iop_desc_get_src_addr(unmap,
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iop_chan,
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src_cnt);
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if (addr == dest)
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continue;
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dma_unmap_page(dev, addr, len,
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DMA_TO_DEVICE);
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}
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}
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desc->group_head = NULL;
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if (iop_desc_is_pq(desc))
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iop_desc_unmap_pq(iop_chan, desc);
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else
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iop_desc_unmap(iop_chan, desc);
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}
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}
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@ -702,6 +746,118 @@ iop_adma_prep_dma_xor_val(struct dma_chan *chan, dma_addr_t *dma_src,
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return sw_desc ? &sw_desc->async_tx : NULL;
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}
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static struct dma_async_tx_descriptor *
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iop_adma_prep_dma_pq(struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
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unsigned int src_cnt, const unsigned char *scf, size_t len,
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unsigned long flags)
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{
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struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
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struct iop_adma_desc_slot *sw_desc, *g;
|
||||
int slot_cnt, slots_per_op;
|
||||
int continue_srcs;
|
||||
|
||||
if (unlikely(!len))
|
||||
return NULL;
|
||||
BUG_ON(len > IOP_ADMA_XOR_MAX_BYTE_COUNT);
|
||||
|
||||
dev_dbg(iop_chan->device->common.dev,
|
||||
"%s src_cnt: %d len: %u flags: %lx\n",
|
||||
__func__, src_cnt, len, flags);
|
||||
|
||||
if (dmaf_p_disabled_continue(flags))
|
||||
continue_srcs = 1+src_cnt;
|
||||
else if (dmaf_continue(flags))
|
||||
continue_srcs = 3+src_cnt;
|
||||
else
|
||||
continue_srcs = 0+src_cnt;
|
||||
|
||||
spin_lock_bh(&iop_chan->lock);
|
||||
slot_cnt = iop_chan_pq_slot_count(len, continue_srcs, &slots_per_op);
|
||||
sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
|
||||
if (sw_desc) {
|
||||
int i;
|
||||
|
||||
g = sw_desc->group_head;
|
||||
iop_desc_set_byte_count(g, iop_chan, len);
|
||||
|
||||
/* even if P is disabled its destination address (bits
|
||||
* [3:0]) must match Q. It is ok if P points to an
|
||||
* invalid address, it won't be written.
|
||||
*/
|
||||
if (flags & DMA_PREP_PQ_DISABLE_P)
|
||||
dst[0] = dst[1] & 0x7;
|
||||
|
||||
iop_desc_set_pq_addr(g, dst);
|
||||
sw_desc->unmap_src_cnt = src_cnt;
|
||||
sw_desc->unmap_len = len;
|
||||
sw_desc->async_tx.flags = flags;
|
||||
for (i = 0; i < src_cnt; i++)
|
||||
iop_desc_set_pq_src_addr(g, i, src[i], scf[i]);
|
||||
|
||||
/* if we are continuing a previous operation factor in
|
||||
* the old p and q values, see the comment for dma_maxpq
|
||||
* in include/linux/dmaengine.h
|
||||
*/
|
||||
if (dmaf_p_disabled_continue(flags))
|
||||
iop_desc_set_pq_src_addr(g, i++, dst[1], 1);
|
||||
else if (dmaf_continue(flags)) {
|
||||
iop_desc_set_pq_src_addr(g, i++, dst[0], 0);
|
||||
iop_desc_set_pq_src_addr(g, i++, dst[1], 1);
|
||||
iop_desc_set_pq_src_addr(g, i++, dst[1], 0);
|
||||
}
|
||||
iop_desc_init_pq(g, i, flags);
|
||||
}
|
||||
spin_unlock_bh(&iop_chan->lock);
|
||||
|
||||
return sw_desc ? &sw_desc->async_tx : NULL;
|
||||
}
|
||||
|
||||
static struct dma_async_tx_descriptor *
|
||||
iop_adma_prep_dma_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
|
||||
unsigned int src_cnt, const unsigned char *scf,
|
||||
size_t len, enum sum_check_flags *pqres,
|
||||
unsigned long flags)
|
||||
{
|
||||
struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
|
||||
struct iop_adma_desc_slot *sw_desc, *g;
|
||||
int slot_cnt, slots_per_op;
|
||||
|
||||
if (unlikely(!len))
|
||||
return NULL;
|
||||
BUG_ON(len > IOP_ADMA_XOR_MAX_BYTE_COUNT);
|
||||
|
||||
dev_dbg(iop_chan->device->common.dev, "%s src_cnt: %d len: %u\n",
|
||||
__func__, src_cnt, len);
|
||||
|
||||
spin_lock_bh(&iop_chan->lock);
|
||||
slot_cnt = iop_chan_pq_zero_sum_slot_count(len, src_cnt + 2, &slots_per_op);
|
||||
sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
|
||||
if (sw_desc) {
|
||||
/* for validate operations p and q are tagged onto the
|
||||
* end of the source list
|
||||
*/
|
||||
int pq_idx = src_cnt;
|
||||
|
||||
g = sw_desc->group_head;
|
||||
iop_desc_init_pq_zero_sum(g, src_cnt+2, flags);
|
||||
iop_desc_set_pq_zero_sum_byte_count(g, len);
|
||||
g->pq_check_result = pqres;
|
||||
pr_debug("\t%s: g->pq_check_result: %p\n",
|
||||
__func__, g->pq_check_result);
|
||||
sw_desc->unmap_src_cnt = src_cnt+2;
|
||||
sw_desc->unmap_len = len;
|
||||
sw_desc->async_tx.flags = flags;
|
||||
while (src_cnt--)
|
||||
iop_desc_set_pq_zero_sum_src_addr(g, src_cnt,
|
||||
src[src_cnt],
|
||||
scf[src_cnt]);
|
||||
iop_desc_set_pq_zero_sum_addr(g, pq_idx, src);
|
||||
}
|
||||
spin_unlock_bh(&iop_chan->lock);
|
||||
|
||||
return sw_desc ? &sw_desc->async_tx : NULL;
|
||||
}
|
||||
|
||||
static void iop_adma_free_chan_resources(struct dma_chan *chan)
|
||||
{
|
||||
struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
|
||||
|
|
@ -1201,6 +1357,13 @@ static int __devinit iop_adma_probe(struct platform_device *pdev)
|
|||
if (dma_has_cap(DMA_XOR_VAL, dma_dev->cap_mask))
|
||||
dma_dev->device_prep_dma_xor_val =
|
||||
iop_adma_prep_dma_xor_val;
|
||||
if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
|
||||
dma_set_maxpq(dma_dev, iop_adma_get_max_pq(), 0);
|
||||
dma_dev->device_prep_dma_pq = iop_adma_prep_dma_pq;
|
||||
}
|
||||
if (dma_has_cap(DMA_PQ_VAL, dma_dev->cap_mask))
|
||||
dma_dev->device_prep_dma_pq_val =
|
||||
iop_adma_prep_dma_pq_val;
|
||||
if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask))
|
||||
dma_dev->device_prep_dma_interrupt =
|
||||
iop_adma_prep_dma_interrupt;
|
||||
|
|
|
|||
Loading…
Reference in New Issue