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drm/amd/display: FW release 1.0.10 

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Anthony Koo 2020-05-01 23:06:03 -04:00 committed by Alex Deucher
parent 474ac4a875
commit 7b8a6362fa
4 changed files with 49 additions and 9 deletions
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2
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
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@ -231,7 +231,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
copy_settings_data->smu_optimizations_en = psr_context->allow_smu_optimizations;
copy_settings_data->frame_delay = psr_context->frame_delay;
copy_settings_data->frame_cap_ind = psr_context->psrFrameCaptureIndicationReq;
copy_settings_data->debug.visual_confirm = dc->dc->debug.visual_confirm == VISUAL_CONFIRM_PSR ?
copy_settings_data->debug.bitfields.visual_confirm = dc->dc->debug.visual_confirm == VISUAL_CONFIRM_PSR ?
true : false;
dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);

12
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
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@ -219,6 +219,7 @@ struct dmub_rb_cmd_dpphy_init {
};
struct dmub_cmd_psr_copy_settings_data {
union dmub_psr_debug_flags debug;
uint16_t psr_level;
uint8_t dpp_inst;
uint8_t mpcc_inst;
@ -231,7 +232,7 @@ struct dmub_cmd_psr_copy_settings_data {
uint8_t smu_optimizations_en;
uint8_t frame_delay;
uint8_t frame_cap_ind;
struct dmub_psr_debug_flags debug;
uint8_t pad[3];
};
struct dmub_rb_cmd_psr_copy_settings {
@ -241,6 +242,7 @@ struct dmub_rb_cmd_psr_copy_settings {
struct dmub_cmd_psr_set_level_data {
uint16_t psr_level;
uint8_t pad[2];
};
struct dmub_rb_cmd_psr_set_level {
@ -262,10 +264,10 @@ struct dmub_rb_cmd_psr_set_version {
};
struct dmub_cmd_abm_set_pipe_data {
uint32_t ramping_boundary;
uint32_t otg_inst;
uint32_t panel_inst;
uint32_t set_pipe_option;
uint8_t otg_inst;
uint8_t panel_inst;
uint8_t set_pipe_option;
uint8_t ramping_boundary; // TODO: Remove this
};
struct dmub_rb_cmd_abm_set_pipe {

35
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd_dal.h
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@ -26,6 +26,11 @@
#ifndef _DMUB_CMD_DAL_H_
#define _DMUB_CMD_DAL_H_
#define NUM_AMBI_LEVEL 5
#define NUM_AGGR_LEVEL 4
#define NUM_POWER_FN_SEGS 8
#define NUM_BL_CURVE_SEGS 16
/*
* Command IDs should be treated as stable ABI.
* Do not reuse or modify IDs.
@ -53,4 +58,34 @@ enum dmub_cmd_abm_type {
DMUB_CMD__ABM_SET_PWM_FRAC = 5,
};
/*
* Parameters for ABM2.4 algorithm.
* Padded explicitly to 32-bit boundary.
*/
struct abm_config_table {
/* Parameters for crgb conversion */
uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B
uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 15B
uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 31B
/* Parameters for custom curve */
uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 47B
uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 79B
uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 111B
uint16_t min_abm_backlight; // 121B
uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 123B
uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 143B
uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 163B
uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 183B
uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 203B
uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 207B
uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 211B
uint8_t min_knee[NUM_AGGR_LEVEL]; // 215B
uint8_t max_knee[NUM_AGGR_LEVEL]; // 219B
uint8_t iir_curve[NUM_AMBI_LEVEL]; // 223B
uint8_t pad3[3]; // 228B
};
#endif /* _DMUB_CMD_DAL_H_ */

9
drivers/gpu/drm/amd/display/dmub/inc/dmub_types.h
View File

@ -63,9 +63,12 @@ union dmub_addr {
uint64_t quad_part;
};
struct dmub_psr_debug_flags {
uint8_t visual_confirm : 1;
uint8_t reserved : 7;
union dmub_psr_debug_flags {
struct {
uint8_t visual_confirm : 1;
} bitfields;
unsigned int u32All;
};
#if defined(__cplusplus)