UbiquitousOS
/
OpenCloudOS-Kernel
mirror of https://gitee.com/OpenCloudOS/OpenCloudOS-Kernel.git
11
0
Fork 0
Code Issues Projects Releases Wiki Activity

ARM: SoC fixes 

I've been bad at collecting fixes this release cycle, so this is
 a fairly large batch that's been trickling in for a while.
 
 It's the usual mix, more or less:
 
 Some of the bigger things fixed:
  - Voltage fix for MMC on TI DRA7 that sometimes would overvoltage cards
  - Regression fixes for D_CAN on am355x
  - i.MX6SX cpuidle fix to deal with wakeup latency (dropped uart chars)
  - DT fixes for some DRA7 variants that don't share the superset of
    blocks on the chip
 
 + The usual mix of stuff -- minor build/warning fixes, Kconfig
 dependencies, and some DT fixlets.
 -----BEGIN PGP SIGNATURE-----
 
 iQJDBAABCAAtFiEElf+HevZ4QCAJmMQ+jBrnPN6EHHcFAl0I67gPHG9sb2ZAbGl4
 b20ubmV0AAoJEIwa5zzehBx3Hf4QAKKdaDz3V0v/+znx13YZdOzW7xXsO8Znd2n8
 L9o86PCh57Auo7/wdYPcNxM0f/HHabnJdFeHQ2d9CZjQu54xOH59G/zpqcdd3zo0
 4DEucZmagZaXrrSjFbh8OTks8ogT+IbSrPHniRenKXc5MhD7Ewlfz3AUMeB3gU+t
 Z1KhA49j5OA2nTSOc8EgjykE2YfejbPwujZ+VROYDpiczYlQb6/TO1JXMSsX/APC
 2LMWlPFtm6NnmiQJEUV8CRl+3X2TBrjjbmOszN2Ra27XV10Te8FMNx5A4vAIH3N5
 KDzfh/zNO6nNgvxdqlnPE7sFXfWs3Nqo62M52hxRoWJap4y83F1S87kgW2vJ6+gm
 HaHo/zEsE3kz8er3Geeobuc7ldL0qEisWZodGJWQnCOfXXAota9xHe5CFiPCCWJ3
 Bouvep7JTA2qrUiu+kW5R+I1v0e2oCLDkfE1f8uZkiv2cDbEagLJfORp4qwAvWs/
 tgOFX6+HtfQr7ZRdgvfgyYJlsRMuP5IeZpUZ7bfsyIcJlG6dBEoqzs590BXNLuTt
 4gxFrSBcVgkHtesusJKpqvMDBF+/xItXq1ggvQU2rpE1XPfIZy9Pv8sbEFsl8UDY
 Abq+eFdt12bdAu2ZjFy+IXmp8KFEgW8w7U5rGDOpMyqzwAOErSw40zFYk1Y94MV2
 ZHvsSNR3
 =pAiT
 -----END PGP SIGNATURE-----

Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC fixes from Olof Johansson:
 "I've been bad at collecting fixes this release cycle, so this is a
  fairly large batch that's been trickling in for a while.

  It's the usual mix, more or less.

  Some of the bigger things fixed:

   - Voltage fix for MMC on TI DRA7 that sometimes would overvoltage
     cards

   - Regression fixes for D_CAN on am355x

   - i.MX6SX cpuidle fix to deal with wakeup latency (dropped uart
     chars)

   - DT fixes for some DRA7 variants that don't share the superset of
     blocks on the chip

  plus the usual mix of stuff: minor build/warning fixes, Kconfig
  dependencies, and some DT fixlets"

* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (28 commits)
  soc: ixp4xx: npe: Fix an IS_ERR() vs NULL check in probe
  ARM: ixp4xx: include irqs.h where needed
  ARM: ixp4xx: mark ixp4xx_irq_setup as __init
  ARM: ixp4xx: don't select SERIAL_OF_PLATFORM
  firmware: trusted_foundations: add ARMv7 dependency
  MAINTAINERS: Change QCOM repo location
  ARM: davinci: da8xx: specify dma_coherent_mask for lcdc
  ARM: davinci: da850-evm: call regulator_has_full_constraints()
  ARM: mvebu_v7_defconfig: fix Ethernet on Clearfog
  ARM: dts: am335x phytec boards: Fix cd-gpios active level
  ARM: dts: dra72x: Disable usb4_tm target module
  arm64: arch_k3: Fix kconfig dependency warning
  ARM: dts: Drop bogus CLKSEL for timer12 on dra7
  MAINTAINERS: Update Stefan Wahren email address
  ARM: dts: bcm: Add missing device_type = "memory" property
  soc: bcm: brcmstb: biuctrl: Register writes require a barrier
  soc: brcmstb: Fix error path for unsupported CPUs
  ARM: dts: dra71x: Disable usb4_tm target module
  ARM: dts: dra71x: Disable rtc target module
  ARM: dts: dra76x: Disable usb4_tm target module
  ...
This commit is contained in:
Linus Torvalds 2019-06-18 10:59:59 -07:00
parent 915ed9320c cd3967bee0
commit 7b306892cc
49 changed files with 127 additions and 63 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
MAINTAINERS
View File

@ -2085,7 +2085,7 @@ F: drivers/tty/serial/msm_serial.c
F: drivers/usb/dwc3/dwc3-qcom.c
F: include/dt-bindings/*/qcom*
F: include/linux/*/qcom*
T: git git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git
T: git git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git
ARM/RADISYS ENP2611 MACHINE SUPPORT
M: Lennert Buytenhek <kernel@wantstofly.org>
@ -3121,7 +3121,7 @@ F: arch/arm/mach-bcm/
BROADCOM BCM2835 ARM ARCHITECTURE
M: Eric Anholt <eric@anholt.net>
M: Stefan Wahren <stefan.wahren@i2se.com>
M: Stefan Wahren <wahrenst@gmx.net>
L: linux-rpi-kernel@lists.infradead.org (moderated for non-subscribers)
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
T: git git://github.com/anholt/linux

2
arch/arm/boot/dts/am335x-pcm-953.dtsi
View File

@ -197,7 +197,7 @@
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
status = "okay";
};

2
arch/arm/boot/dts/am335x-wega.dtsi
View File

@ -157,7 +157,7 @@
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
status = "okay";
};

14
arch/arm/boot/dts/am33xx-l4.dtsi
View File

@ -1759,11 +1759,10 @@
target-module@cc000 { /* 0x481cc000, ap 60 46.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "d_can0";
reg = <0xcc000 0x4>;
reg-names = "rev";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN0_CLKCTRL 0>;
clock-names = "fck";
clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN0_CLKCTRL 0>,
<&dcan0_fck>;
clock-names = "fck", "osc";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xcc000 0x2000>;
@ -1782,11 +1781,10 @@
target-module@d0000 { /* 0x481d0000, ap 62 42.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "d_can1";
reg = <0xd0000 0x4>;
reg-names = "rev";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN1_CLKCTRL 0>;
clock-names = "fck";
clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN1_CLKCTRL 0>,
<&dcan1_fck>;
clock-names = "fck", "osc";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xd0000 0x2000>;

4
arch/arm/boot/dts/am437x-l4.dtsi
View File

@ -1575,8 +1575,6 @@
target-module@cc000 { /* 0x481cc000, ap 50 46.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "d_can0";
reg = <0xcc000 0x4>;
reg-names = "rev";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN0_CLKCTRL 0>;
clock-names = "fck";
@ -1596,8 +1594,6 @@
target-module@d0000 { /* 0x481d0000, ap 52 3a.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "d_can1";
reg = <0xd0000 0x4>;
reg-names = "rev";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN1_CLKCTRL 0>;
clock-names = "fck";

1
arch/arm/boot/dts/am57xx-idk-common.dtsi
View File

@ -420,6 +420,7 @@
vqmmc-supply = <&ldo1_reg>;
bus-width = <4>;
cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
no-1-8-v;
};
&mmc2 {

1
arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts
View File

@ -20,6 +20,7 @@
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x08000000>;
};

1
arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts
View File

@ -20,6 +20,7 @@
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x08000000>;
};

1
arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
View File

@ -20,6 +20,7 @@
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x18000000>;
};

1
arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts
View File

@ -17,6 +17,7 @@
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};

1
arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts
View File

@ -18,6 +18,7 @@
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};

1
arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts
View File

@ -16,6 +16,7 @@
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};

1
arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts
View File

@ -20,6 +20,7 @@
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};

1
arch/arm/boot/dts/bcm4708-netgear-r6250.dts
View File

@ -21,6 +21,7 @@
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x08000000>;
};

1
arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts
View File

@ -20,6 +20,7 @@
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x08000000>;
};

1
arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
View File

@ -20,6 +20,7 @@
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x08000000>;
};

1
arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts
View File

@ -20,6 +20,7 @@
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x08000000>;
};

1
arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts
View File

@ -20,6 +20,7 @@
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x18000000>;
};

1
arch/arm/boot/dts/bcm4709-linksys-ea9200.dts
View File

@ -17,6 +17,7 @@
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x08000000>;
};

1
arch/arm/boot/dts/bcm4709-netgear-r7000.dts
View File

@ -20,6 +20,7 @@
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x08000000>;
};

1
arch/arm/boot/dts/bcm4709-netgear-r8000.dts
View File

@ -31,6 +31,7 @@
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x08000000>;
};

1
arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts
View File

@ -16,6 +16,7 @@
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};

1
arch/arm/boot/dts/bcm47094-phicomm-k3.dts
View File

@ -14,6 +14,7 @@
model = "Phicomm K3";
memory {
device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x18000000>;
};

1
arch/arm/boot/dts/bcm94708.dts
View File

@ -39,6 +39,7 @@
compatible = "brcm,bcm94708", "brcm,bcm4708";
memory {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};
};

1
arch/arm/boot/dts/bcm94709.dts
View File

@ -39,6 +39,7 @@
compatible = "brcm,bcm94709", "brcm,bcm4709", "brcm,bcm4708";
memory {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};
};

1
arch/arm/boot/dts/bcm963138dvt.dts
View File

@ -17,6 +17,7 @@
};
memory {
device_type = "memory";
reg = <0x0 0x08000000>;
};

4
arch/arm/boot/dts/dra7-l4.dtsi
View File

@ -3543,7 +3543,7 @@
};
};
target-module@38000 { /* 0x48838000, ap 29 12.0 */
rtctarget: target-module@38000 { /* 0x48838000, ap 29 12.0 */
compatible = "ti,sysc-omap4-simple", "ti,sysc";
ti,hwmods = "rtcss";
reg = <0x38074 0x4>,
@ -4450,8 +4450,6 @@
timer12: timer@0 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x80>;
clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER12_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-alwon;
ti,timer-secure;

2
arch/arm/boot/dts/dra71-evm.dts
View File

@ -6,7 +6,7 @@
* published by the Free Software Foundation.
*/
#include "dra72-evm-common.dtsi"
#include "dra71x.dtsi"
#include "dra7-mmc-iodelay.dtsi"
#include "dra72x-mmc-iodelay.dtsi"
#include <dt-bindings/net/ti-dp83867.h>

17
arch/arm/boot/dts/dra71x.dtsi Normal file
View File

@ -0,0 +1,17 @@
/*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "dra72-evm-common.dtsi"
&rtctarget {
status = "disabled";
};
&usb4_tm {
status = "disabled";
};

4
arch/arm/boot/dts/dra72x.dtsi
View File

@ -62,3 +62,7 @@
&pcie2_rc {
compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie";
};
&usb4_tm {
status = "disabled";
};

40
arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi
View File

@ -22,7 +22,7 @@
*
* Datamanual Revisions:
*
* DRA76x Silicon Revision 1.0: SPRS993A, Revised July 2017
* DRA76x Silicon Revision 1.0: SPRS993E, Revised December 2018
*
*/
@ -169,25 +169,25 @@
/* Corresponds to MMC2_HS200_MANUAL1 in datamanual */
mmc2_iodelay_hs200_conf: mmc2_iodelay_hs200_conf {
pinctrl-pin-array = <
0x190 A_DELAY_PS(384) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */
0x194 A_DELAY_PS(0) G_DELAY_PS(174) /* CFG_GPMC_A19_OUT */
0x1a8 A_DELAY_PS(410) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */
0x1ac A_DELAY_PS(85) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */
0x1b4 A_DELAY_PS(468) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */
0x1b8 A_DELAY_PS(139) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */
0x1c0 A_DELAY_PS(676) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */
0x1c4 A_DELAY_PS(69) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */
0x1d0 A_DELAY_PS(1062) G_DELAY_PS(154) /* CFG_GPMC_A23_OUT */
0x1d8 A_DELAY_PS(640) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */
0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */
0x1e4 A_DELAY_PS(356) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */
0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */
0x1f0 A_DELAY_PS(579) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */
0x1f4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */
0x1fc A_DELAY_PS(435) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */
0x200 A_DELAY_PS(36) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */
0x364 A_DELAY_PS(759) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */
0x368 A_DELAY_PS(72) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */
0x190 A_DELAY_PS(384) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */
0x194 A_DELAY_PS(350) G_DELAY_PS(174) /* CFG_GPMC_A19_OUT */
0x1a8 A_DELAY_PS(410) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */
0x1ac A_DELAY_PS(335) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */
0x1b4 A_DELAY_PS(468) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */
0x1b8 A_DELAY_PS(339) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */
0x1c0 A_DELAY_PS(676) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */
0x1c4 A_DELAY_PS(219) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */
0x1d0 A_DELAY_PS(1062) G_DELAY_PS(154) /* CFG_GPMC_A23_OUT */
0x1d8 A_DELAY_PS(640) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */
0x1dc A_DELAY_PS(150) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */
0x1e4 A_DELAY_PS(356) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */
0x1e8 A_DELAY_PS(150) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */
0x1f0 A_DELAY_PS(579) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */
0x1f4 A_DELAY_PS(200) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */
0x1fc A_DELAY_PS(435) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */
0x200 A_DELAY_PS(236) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */
0x364 A_DELAY_PS(759) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */
0x368 A_DELAY_PS(372) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */
>;
};

8
arch/arm/boot/dts/dra76x.dtsi
View File

@ -81,3 +81,11 @@
reg = <0x3fc>;
};
};
&rtctarget {
status = "disabled";
};
&usb4_tm {
status = "disabled";
};

1
arch/arm/configs/mvebu_v7_defconfig
View File

@ -131,6 +131,7 @@ CONFIG_MV_XOR=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_MEMORY=y
CONFIG_PWM=y
CONFIG_PHY_MVEBU_A38X_COMPHY=y
CONFIG_EXT4_FS=y
CONFIG_ISO9660_FS=y
CONFIG_JOLIET=y

2
arch/arm/mach-davinci/board-da850-evm.c
View File

@ -1480,6 +1480,8 @@ static __init void da850_evm_init(void)
if (ret)
pr_warn("%s: dsp/rproc registration failed: %d\n",
__func__, ret);
regulator_has_full_constraints();
}
#ifdef CONFIG_SERIAL_8250_CONSOLE

3
arch/arm/mach-davinci/devices-da8xx.c
View File

@ -683,6 +683,9 @@ static struct platform_device da8xx_lcdc_device = {
.id = 0,
.num_resources = ARRAY_SIZE(da8xx_lcdc_resources),
.resource = da8xx_lcdc_resources,
.dev = {
.coherent_dma_mask = DMA_BIT_MASK(32),
}
};
int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)

3
arch/arm/mach-imx/cpuidle-imx6sx.c
View File

@ -15,6 +15,7 @@
#include "common.h"
#include "cpuidle.h"
#include "hardware.h"
static int imx6sx_idle_finish(unsigned long val)
{
@ -110,7 +111,7 @@ int __init imx6sx_cpuidle_init(void)
* except for power up sw2iso which need to be
* larger than LDO ramp up time.
*/
imx_gpc_set_arm_power_up_timing(0xf, 1);
imx_gpc_set_arm_power_up_timing(cpu_is_imx6sx() ? 0xf : 0x2, 1);
imx_gpc_set_arm_power_down_timing(1, 1);
return cpuidle_register(&imx6sx_cpuidle_driver, NULL);

1
arch/arm/mach-ixp4xx/Kconfig
View File

@ -13,7 +13,6 @@ config MACH_IXP4XX_OF
select I2C
select I2C_IOP3XX
select PCI
select SERIAL_OF_PLATFORM
select TIMER_OF
select USE_OF
help

2
arch/arm/mach-ixp4xx/goramo_mlr.c
View File

@ -18,6 +18,8 @@
#include <asm/mach/pci.h>
#include <asm/system_info.h>
#include "irqs.h"
#define SLOT_ETHA 0x0B /* IDSEL = AD21 */
#define SLOT_ETHB 0x0C /* IDSEL = AD20 */
#define SLOT_MPCI 0x0D /* IDSEL = AD19 */

2
arch/arm/mach-ixp4xx/miccpt-pci.c
View File

@ -25,6 +25,8 @@
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include "irqs.h"
#define MAX_DEV 4
#define IRQ_LINES 4

2
arch/arm/mach-ixp4xx/omixp-setup.c
View File

@ -27,6 +27,8 @@
#include <mach/hardware.h>
#include "irqs.h"
static struct resource omixp_flash_resources[] = {
{
.flags = IORESOURCE_MEM,

2
arch/arm/mach-ixp4xx/vulcan-pci.c
View File

@ -21,6 +21,8 @@
#include <asm/mach/pci.h>
#include <asm/mach-types.h>
#include "irqs.h"
/* PCI controller GPIO to IRQ pin mappings */
#define INTA 2
#define INTB 3

2
arch/arm/mach-ixp4xx/vulcan-setup.c
View File

@ -22,6 +22,8 @@
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include "irqs.h"
static struct flash_platform_data vulcan_flash_data = {
.map_name = "cfi_probe",
.width = 2,

2
arch/arm64/Kconfig.platforms
View File

@ -89,6 +89,7 @@ config ARCH_K3
bool "Texas Instruments Inc. K3 multicore SoC architecture"
select PM_GENERIC_DOMAINS if PM
select MAILBOX
select SOC_TI
select TI_MESSAGE_MANAGER
select TI_SCI_PROTOCOL
select TI_SCI_INTR_IRQCHIP
@ -168,6 +169,7 @@ config ARCH_MXC
select IMX_GPCV2_PM_DOMAINS
select PM
select PM_GENERIC_DOMAINS
select SOC_BUS
help
This enables support for the ARMv8 based SoCs in the
NXP i.MX family.

23
drivers/bus/ti-sysc.c
View File

@ -660,12 +660,6 @@ static int sysc_check_registers(struct sysc *ddata)
nr_regs++;
}
if (nr_regs < 1) {
dev_err(ddata->dev, "missing registers\n");
return -EINVAL;
}
if (nr_matches > nr_regs) {
dev_err(ddata->dev, "overlapping registers: (%i/%i)",
nr_regs, nr_matches);
@ -691,12 +685,18 @@ static int sysc_ioremap(struct sysc *ddata)
{
int size;
size = max3(ddata->offsets[SYSC_REVISION],
ddata->offsets[SYSC_SYSCONFIG],
ddata->offsets[SYSC_SYSSTATUS]);
if (ddata->offsets[SYSC_REVISION] < 0 &&
ddata->offsets[SYSC_SYSCONFIG] < 0 &&
ddata->offsets[SYSC_SYSSTATUS] < 0) {
size = ddata->module_size;
} else {
size = max3(ddata->offsets[SYSC_REVISION],
ddata->offsets[SYSC_SYSCONFIG],
ddata->offsets[SYSC_SYSSTATUS]);
if (size < 0 || (size + sizeof(u32)) > ddata->module_size)
return -EINVAL;
if ((size + sizeof(u32)) > ddata->module_size)
return -EINVAL;
}
ddata->module_va = devm_ioremap(ddata->dev,
ddata->module_pa,
@ -1128,7 +1128,6 @@ static const struct sysc_revision_quirk sysc_revision_quirks[] = {
SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902,
0xffff00f0, 0),
SYSC_QUIRK("dcan", 0, 0, -1, -1, 0xffffffff, 0xffffffff, 0),
SYSC_QUIRK("dcan", 0, 0, -1, -1, 0x00001401, 0xffffffff, 0),
SYSC_QUIRK("dmic", 0, 0, 0x10, -1, 0x50010000, 0xffffffff, 0),
SYSC_QUIRK("dwc3", 0, 0, 0x10, -1, 0x500a0200, 0xffffffff, 0),
SYSC_QUIRK("epwmss", 0, 0, 0x4, -1, 0x47400001, 0xffffffff, 0),

2
drivers/firmware/Kconfig
View File

@ -256,7 +256,7 @@ config TI_SCI_PROTOCOL
config TRUSTED_FOUNDATIONS
bool "Trusted Foundations secure monitor support"
depends on ARM
depends on ARM && CPU_V7
help
Some devices (including most early Tegra-based consumer devices on
the market) are booted with the Trusted Foundations secure monitor

3
drivers/firmware/imx/imx-scu-irq.c
View File

@ -100,6 +100,9 @@ int imx_scu_irq_group_enable(u8 group, u32 mask, u8 enable)
struct imx_sc_rpc_msg *hdr = &msg.hdr;
int ret;
if (!imx_sc_irq_ipc_handle)
return -EPROBE_DEFER;
hdr->ver = IMX_SC_RPC_VERSION;
hdr->svc = IMX_SC_RPC_SVC_IRQ;
hdr->func = IMX_SC_IRQ_FUNC_ENABLE;

8
drivers/irqchip/irq-ixp4xx.c
View File

@ -252,10 +252,10 @@ static const struct ixp4xx_irq_chunk ixp4xx_irq_chunks[] = {
* @fwnode: Corresponding fwnode abstraction for this controller
* @is_356: if this is an IXP43x, IXP45x or IXP46x SoC variant
*/
static int ixp4xx_irq_setup(struct ixp4xx_irq *ixi,
void __iomem *irqbase,
struct fwnode_handle *fwnode,
bool is_356)
static int __init ixp4xx_irq_setup(struct ixp4xx_irq *ixi,
void __iomem *irqbase,
struct fwnode_handle *fwnode,
bool is_356)
{
int nr_irqs;

6
drivers/soc/bcm/brcmstb/biuctrl.c
View File

@ -48,7 +48,7 @@ static inline void cbc_writel(u32 val, int reg)
if (offset == -1)
return;
writel_relaxed(val, cpubiuctrl_base + offset);
writel(val, cpubiuctrl_base + offset);
}
enum cpubiuctrl_regs {
@ -238,7 +238,9 @@ static int __init brcmstb_biuctrl_init(void)
if (!np)
return 0;
setup_hifcpubiuctrl_regs(np);
ret = setup_hifcpubiuctrl_regs(np);
if (ret)
return ret;
ret = mcp_write_pairing_set();
if (ret) {

4
drivers/soc/ixp4xx/ixp4xx-npe.c
View File

@ -695,8 +695,8 @@ static int ixp4xx_npe_probe(struct platform_device *pdev)
continue; /* NPE already disabled or not present */
}
npe->regs = devm_ioremap_resource(dev, res);
if (!npe->regs)
return -ENOMEM;
if (IS_ERR(npe->regs))
return PTR_ERR(npe->regs);
if (npe_reset(npe)) {
dev_info(dev, "NPE%d at 0x%08x-0x%08x does not reset\n",