OMAP4: DSS2: HDMI: Move pll and video configuration
As the pll and the video configuration info are part of the ip_data, pll and video structures are moved to the ip_data structure. Also the pll and video configuration functions are modified accordingly to take care of the structure movement. Signed-off-by: Mythri P K <mythripk@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This commit is contained in:
Mythri P K
Tomi Valkeinen
parent
95a8aeb6c5
commit
7b27da5483
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@ -155,6 +155,13 @@ struct dsi_clock_info {
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bool use_sys_clk;
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};
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enum hdmi_clk_refsel {
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HDMI_REFSEL_PCLK = 0,
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HDMI_REFSEL_REF1 = 1,
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HDMI_REFSEL_REF2 = 2,
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HDMI_REFSEL_SYSCLK = 3
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};
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/* HDMI PLL structure */
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struct hdmi_pll_info {
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u16 regn;
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@ -163,6 +170,7 @@ struct hdmi_pll_info {
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u16 regm2;
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u16 regsd;
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u16 dcofreq;
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enum hdmi_clk_refsel refsel;
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};
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struct seq_file;
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@ -59,7 +59,6 @@ static struct {
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u8 edid[HDMI_EDID_MAX_LENGTH];
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u8 edid_set;
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bool custom_set;
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struct hdmi_config cfg;
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struct clk *sys_clk;
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} hdmi;
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@ -229,12 +228,11 @@ int hdmi_init_display(struct omap_dss_device *dssdev)
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return 0;
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}
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static int hdmi_pll_init(struct hdmi_ip_data *ip_data,
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enum hdmi_clk_refsel refsel, int dcofreq,
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struct hdmi_pll_info *fmt, u16 sd)
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static int hdmi_pll_init(struct hdmi_ip_data *ip_data)
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{
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u32 r;
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void __iomem *pll_base = hdmi_pll_base(ip_data);
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struct hdmi_pll_info *fmt = &ip_data->pll_data;
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/* PLL start always use manual mode */
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REG_FLD_MOD(pll_base, PLLCTRL_PLL_CONTROL, 0x0, 0, 0);
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@ -250,10 +248,11 @@ static int hdmi_pll_init(struct hdmi_ip_data *ip_data,
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r = FLD_MOD(r, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */
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r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */
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r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */
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r = FLD_MOD(r, fmt->refsel, 22, 21); /* REFSEL */
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if (dcofreq) {
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if (fmt->dcofreq) {
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/* divider programming for frequency beyond 1000Mhz */
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REG_FLD_MOD(pll_base, PLLCTRL_CFG3, sd, 17, 10);
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REG_FLD_MOD(pll_base, PLLCTRL_CFG3, fmt->regsd, 17, 10);
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r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */
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} else {
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r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */
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@ -379,11 +378,9 @@ static int hdmi_phy_init(struct hdmi_ip_data *ip_data)
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return 0;
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}
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static int hdmi_pll_program(struct hdmi_ip_data *ip_data,
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struct hdmi_pll_info *fmt)
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static int hdmi_pll_program(struct hdmi_ip_data *ip_data)
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{
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u16 r = 0;
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enum hdmi_clk_refsel refsel;
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r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_ALLOFF);
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if (r)
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@ -397,9 +394,7 @@ static int hdmi_pll_program(struct hdmi_ip_data *ip_data,
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if (r)
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return r;
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refsel = HDMI_REFSEL_SYSCLK;
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r = hdmi_pll_init(ip_data, refsel, fmt->dcofreq, fmt, fmt->regsd);
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r = hdmi_pll_init(ip_data);
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if (r)
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return r;
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@ -1015,8 +1010,7 @@ static void hdmi_wp_video_config_timing(struct hdmi_ip_data *ip_data,
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hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_V, timing_v);
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}
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static void hdmi_basic_configure(struct hdmi_ip_data *ip_data,
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struct hdmi_config *cfg)
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static void hdmi_basic_configure(struct hdmi_ip_data *ip_data)
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{
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/* HDMI */
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struct omap_video_timings video_timing;
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@ -1026,6 +1020,7 @@ static void hdmi_basic_configure(struct hdmi_ip_data *ip_data,
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struct hdmi_core_infoframe_avi avi_cfg;
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struct hdmi_core_video_config v_core_cfg;
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struct hdmi_core_packet_enable_repeat repeat_cfg;
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struct hdmi_config *cfg = &ip_data->cfg;
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hdmi_wp_init(&video_timing, &video_format,
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&video_interface);
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@ -1034,8 +1029,7 @@ static void hdmi_basic_configure(struct hdmi_ip_data *ip_data,
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&avi_cfg,
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&repeat_cfg);
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hdmi_wp_video_init_format(&video_format,
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&video_timing, cfg);
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hdmi_wp_video_init_format(&video_format, &video_timing, cfg);
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hdmi_wp_video_config_timing(ip_data, &video_timing);
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@ -1154,6 +1148,9 @@ static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
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pi->dcofreq = phy > 1000 * 100;
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pi->regsd = ((pi->regm * clkin / 10) / ((pi->regn + 1) * 250) + 5) / 10;
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/* Set the reference clock to sysclk reference */
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pi->refsel = HDMI_REFSEL_SYSCLK;
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DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf);
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DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
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}
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@ -1161,7 +1158,6 @@ static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
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static int hdmi_power_on(struct omap_dss_device *dssdev)
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{
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int r, code = 0;
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struct hdmi_pll_info pll_data;
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struct omap_video_timings *p;
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unsigned long phy;
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@ -1183,16 +1179,16 @@ static int hdmi_power_on(struct omap_dss_device *dssdev)
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}
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code = get_timings_index();
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dssdev->panel.timings = cea_vesa_timings[code].timings;
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update_hdmi_timings(&hdmi.cfg, p, code);
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update_hdmi_timings(&hdmi.ip_data.cfg, p, code);
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phy = p->pixel_clock;
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hdmi_compute_pll(dssdev, phy, &pll_data);
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hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data);
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hdmi_wp_video_start(&hdmi.ip_data, 0);
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/* config the PLL and PHY hdmi_set_pll_pwrfirst */
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r = hdmi_pll_program(&hdmi.ip_data, &pll_data);
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r = hdmi_pll_program(&hdmi.ip_data);
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if (r) {
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DSSDBG("Failed to lock PLL\n");
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goto err;
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@ -1204,9 +1200,9 @@ static int hdmi_power_on(struct omap_dss_device *dssdev)
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goto err;
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}
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hdmi.cfg.cm.mode = hdmi.mode;
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hdmi.cfg.cm.code = hdmi.code;
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hdmi_basic_configure(&hdmi.ip_data, &hdmi.cfg);
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hdmi.ip_data.cfg.cm.mode = hdmi.mode;
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hdmi.ip_data.cfg.cm.code = hdmi.code;
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hdmi_basic_configure(&hdmi.ip_data);
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/* Make selection of HDMI in DSS */
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dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
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@ -218,13 +218,6 @@ enum hdmi_pll_pwr {
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HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3
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};
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enum hdmi_clk_refsel {
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HDMI_REFSEL_PCLK = 0,
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HDMI_REFSEL_REF1 = 1,
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HDMI_REFSEL_REF2 = 2,
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HDMI_REFSEL_SYSCLK = 3
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};
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enum hdmi_core_inputbus_width {
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HDMI_INPUT_8BIT = 0,
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HDMI_INPUT_10BIT = 1,
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@ -558,14 +551,6 @@ struct hdmi_video_interface {
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int tm; /* Timing mode */
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};
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struct hdmi_ip_data {
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void __iomem *base_wp; /* HDMI wrapper */
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unsigned long core_sys_offset;
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unsigned long core_av_offset;
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unsigned long pll_offset;
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unsigned long phy_offset;
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};
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struct hdmi_cm {
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int code;
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int mode;
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@ -577,6 +562,16 @@ struct hdmi_config {
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struct hdmi_cm cm;
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};
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struct hdmi_ip_data {
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void __iomem *base_wp; /* HDMI wrapper */
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unsigned long core_sys_offset;
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unsigned long core_av_offset;
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unsigned long pll_offset;
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unsigned long phy_offset;
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struct hdmi_config cfg;
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struct hdmi_pll_info pll_data;
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};
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struct hdmi_audio_format {
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enum hdmi_stereo_channels stereo_channels;
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u8 active_chnnls_msk;
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