drm/amd/powerplay: add DFCstate control pptable func for arct
This is the callback function that is going to be invoked when amdgpu_dpm_set_df_cstate is called to toggle DFCstate Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -127,6 +127,7 @@ static struct smu_11_0_cmn2aisc_mapping arcturus_message_map[SMU_MSG_MAX_COUNT]
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MSG_MAP(WaflTest, PPSMC_MSG_WaflTest),
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MSG_MAP(SetXgmiMode, PPSMC_MSG_SetXgmiMode),
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MSG_MAP(SetMemoryChannelEnable, PPSMC_MSG_SetMemoryChannelEnable),
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MSG_MAP(DFCstateControl, PPSMC_MSG_DFCstateControl),
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};
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static struct smu_11_0_cmn2aisc_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
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@ -2214,6 +2215,27 @@ static uint32_t arcturus_get_pptable_power_limit(struct smu_context *smu)
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return pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
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}
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static int arcturus_set_df_cstate(struct smu_context *smu,
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enum pp_df_cstate state)
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{
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uint32_t smu_version;
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int ret;
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ret = smu_get_smc_version(smu, NULL, &smu_version);
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if (ret) {
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pr_err("Failed to get smu version!\n");
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return ret;
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}
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/* PPSMC_MSG_DFCstateControl is supported by 54.15.0 and onwards */
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if (smu_version < 0x360F00) {
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pr_err("DFCstateControl is only supported by PMFW 54.15.0 and onwards\n");
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return -EINVAL;
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}
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return smu_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state);
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}
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static const struct pptable_funcs arcturus_ppt_funcs = {
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/* translate smu index into arcturus specific index */
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.get_smu_msg_index = arcturus_get_smu_msg_index,
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@ -2307,6 +2329,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
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.set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
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.override_pcie_parameters = smu_v11_0_override_pcie_parameters,
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.get_pptable_power_limit = arcturus_get_pptable_power_limit,
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.set_df_cstate = arcturus_set_df_cstate,
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};
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void arcturus_set_ppt_funcs(struct smu_context *smu)
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