Merge branch 'enetc-mac-merge-prep'
Vladimir Oltean says: ==================== ENETC MAC Merge cleanup This is a preparatory patch set for MAC Merge layer support in enetc via ethtool. It does the following: - consolidates a software lockstep register write procedure for the pMAC - detects per-port frame preemption capability and only writes pMAC registers if a pMAC exists - stops enabling the pMAC by default Additionally, I noticed some build warnings in the driver which are new in this kernel version, so patch 1/6 fixes those. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
commit
7a98143118
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@ -1,7 +1,16 @@
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||||||
# SPDX-License-Identifier: GPL-2.0
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# SPDX-License-Identifier: GPL-2.0
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||||||
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config FSL_ENETC_CORE
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||||||
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tristate
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||||||
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help
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This module supports common functionality between the PF and VF
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||||||
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drivers for the NXP ENETC controller.
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If compiled as module (M), the module name is fsl-enetc-core.
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config FSL_ENETC
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config FSL_ENETC
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tristate "ENETC PF driver"
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tristate "ENETC PF driver"
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depends on PCI_MSI
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depends on PCI_MSI
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select FSL_ENETC_CORE
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select FSL_ENETC_IERB
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select FSL_ENETC_IERB
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select FSL_ENETC_MDIO
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select FSL_ENETC_MDIO
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select PHYLINK
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select PHYLINK
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@ -17,6 +26,7 @@ config FSL_ENETC
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config FSL_ENETC_VF
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config FSL_ENETC_VF
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tristate "ENETC VF driver"
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tristate "ENETC VF driver"
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depends on PCI_MSI
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depends on PCI_MSI
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select FSL_ENETC_CORE
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select FSL_ENETC_MDIO
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select FSL_ENETC_MDIO
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select PHYLINK
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select PHYLINK
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select DIMLIB
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select DIMLIB
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|
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@ -1,14 +1,15 @@
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# SPDX-License-Identifier: GPL-2.0
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# SPDX-License-Identifier: GPL-2.0
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common-objs := enetc.o enetc_cbdr.o enetc_ethtool.o
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obj-$(CONFIG_FSL_ENETC_CORE) += fsl-enetc-core.o
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fsl-enetc-core-y := enetc.o enetc_cbdr.o enetc_ethtool.o
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obj-$(CONFIG_FSL_ENETC) += fsl-enetc.o
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obj-$(CONFIG_FSL_ENETC) += fsl-enetc.o
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fsl-enetc-y := enetc_pf.o $(common-objs)
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fsl-enetc-y := enetc_pf.o
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fsl-enetc-$(CONFIG_PCI_IOV) += enetc_msg.o
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fsl-enetc-$(CONFIG_PCI_IOV) += enetc_msg.o
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fsl-enetc-$(CONFIG_FSL_ENETC_QOS) += enetc_qos.o
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fsl-enetc-$(CONFIG_FSL_ENETC_QOS) += enetc_qos.o
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obj-$(CONFIG_FSL_ENETC_VF) += fsl-enetc-vf.o
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obj-$(CONFIG_FSL_ENETC_VF) += fsl-enetc-vf.o
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fsl-enetc-vf-y := enetc_vf.o $(common-objs)
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fsl-enetc-vf-y := enetc_vf.o
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obj-$(CONFIG_FSL_ENETC_IERB) += fsl-enetc-ierb.o
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obj-$(CONFIG_FSL_ENETC_IERB) += fsl-enetc-ierb.o
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fsl-enetc-ierb-y := enetc_ierb.o
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fsl-enetc-ierb-y := enetc_ierb.o
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@ -11,6 +11,20 @@
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#include <net/pkt_sched.h>
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#include <net/pkt_sched.h>
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#include <net/tso.h>
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#include <net/tso.h>
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u32 enetc_port_mac_rd(struct enetc_si *si, u32 reg)
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{
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return enetc_port_rd(&si->hw, reg);
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}
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EXPORT_SYMBOL_GPL(enetc_port_mac_rd);
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void enetc_port_mac_wr(struct enetc_si *si, u32 reg, u32 val)
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{
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enetc_port_wr(&si->hw, reg, val);
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if (si->hw_features & ENETC_SI_F_QBU)
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enetc_port_wr(&si->hw, reg + ENETC_PMAC_OFFSET, val);
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}
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EXPORT_SYMBOL_GPL(enetc_port_mac_wr);
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static int enetc_num_stack_tx_queues(struct enetc_ndev_priv *priv)
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static int enetc_num_stack_tx_queues(struct enetc_ndev_priv *priv)
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{
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{
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int num_tx_rings = priv->num_tx_rings;
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int num_tx_rings = priv->num_tx_rings;
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@ -243,8 +257,8 @@ static int enetc_map_tx_buffs(struct enetc_bdr *tx_ring, struct sk_buff *skb)
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if (udp)
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if (udp)
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val |= ENETC_PM0_SINGLE_STEP_CH;
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val |= ENETC_PM0_SINGLE_STEP_CH;
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enetc_port_wr(hw, ENETC_PM0_SINGLE_STEP, val);
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enetc_port_mac_wr(priv->si, ENETC_PM0_SINGLE_STEP,
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enetc_port_wr(hw, ENETC_PM1_SINGLE_STEP, val);
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val);
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} else if (do_twostep_tstamp) {
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} else if (do_twostep_tstamp) {
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skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
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skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
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e_flags |= ENETC_TXBD_E_FLAGS_TWO_STEP_PTP;
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e_flags |= ENETC_TXBD_E_FLAGS_TWO_STEP_PTP;
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@ -651,6 +665,7 @@ netdev_tx_t enetc_xmit(struct sk_buff *skb, struct net_device *ndev)
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return enetc_start_xmit(skb, ndev);
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return enetc_start_xmit(skb, ndev);
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}
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}
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EXPORT_SYMBOL_GPL(enetc_xmit);
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static irqreturn_t enetc_msix(int irq, void *data)
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static irqreturn_t enetc_msix(int irq, void *data)
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{
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{
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@ -1388,6 +1403,7 @@ int enetc_xdp_xmit(struct net_device *ndev, int num_frames,
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return xdp_tx_frm_cnt;
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return xdp_tx_frm_cnt;
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}
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}
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EXPORT_SYMBOL_GPL(enetc_xdp_xmit);
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static void enetc_map_rx_buff_to_xdp(struct enetc_bdr *rx_ring, int i,
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static void enetc_map_rx_buff_to_xdp(struct enetc_bdr *rx_ring, int i,
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struct xdp_buff *xdp_buff, u16 size)
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struct xdp_buff *xdp_buff, u16 size)
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@ -1711,9 +1727,13 @@ void enetc_get_si_caps(struct enetc_si *si)
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if (val & ENETC_SIPCAPR0_QBV)
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if (val & ENETC_SIPCAPR0_QBV)
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si->hw_features |= ENETC_SI_F_QBV;
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si->hw_features |= ENETC_SI_F_QBV;
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if (val & ENETC_SIPCAPR0_QBU)
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si->hw_features |= ENETC_SI_F_QBU;
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if (val & ENETC_SIPCAPR0_PSFP)
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if (val & ENETC_SIPCAPR0_PSFP)
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si->hw_features |= ENETC_SI_F_PSFP;
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si->hw_features |= ENETC_SI_F_PSFP;
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}
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}
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EXPORT_SYMBOL_GPL(enetc_get_si_caps);
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static int enetc_dma_alloc_bdr(struct enetc_bdr_resource *res)
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static int enetc_dma_alloc_bdr(struct enetc_bdr_resource *res)
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{
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{
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@ -2029,6 +2049,7 @@ int enetc_configure_si(struct enetc_ndev_priv *priv)
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return 0;
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return 0;
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}
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}
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EXPORT_SYMBOL_GPL(enetc_configure_si);
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void enetc_init_si_rings_params(struct enetc_ndev_priv *priv)
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void enetc_init_si_rings_params(struct enetc_ndev_priv *priv)
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{
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{
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@ -2048,6 +2069,7 @@ void enetc_init_si_rings_params(struct enetc_ndev_priv *priv)
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priv->ic_mode = ENETC_IC_RX_ADAPTIVE | ENETC_IC_TX_MANUAL;
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priv->ic_mode = ENETC_IC_RX_ADAPTIVE | ENETC_IC_TX_MANUAL;
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priv->tx_ictt = ENETC_TXIC_TIMETHR;
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priv->tx_ictt = ENETC_TXIC_TIMETHR;
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}
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}
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EXPORT_SYMBOL_GPL(enetc_init_si_rings_params);
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int enetc_alloc_si_resources(struct enetc_ndev_priv *priv)
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int enetc_alloc_si_resources(struct enetc_ndev_priv *priv)
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{
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{
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@ -2060,11 +2082,13 @@ int enetc_alloc_si_resources(struct enetc_ndev_priv *priv)
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return 0;
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return 0;
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}
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}
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EXPORT_SYMBOL_GPL(enetc_alloc_si_resources);
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void enetc_free_si_resources(struct enetc_ndev_priv *priv)
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void enetc_free_si_resources(struct enetc_ndev_priv *priv)
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{
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{
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kfree(priv->cls_rules);
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kfree(priv->cls_rules);
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}
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}
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EXPORT_SYMBOL_GPL(enetc_free_si_resources);
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static void enetc_setup_txbdr(struct enetc_hw *hw, struct enetc_bdr *tx_ring)
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static void enetc_setup_txbdr(struct enetc_hw *hw, struct enetc_bdr *tx_ring)
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{
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{
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@ -2426,6 +2450,7 @@ void enetc_start(struct net_device *ndev)
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netif_tx_start_all_queues(ndev);
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netif_tx_start_all_queues(ndev);
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}
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}
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EXPORT_SYMBOL_GPL(enetc_start);
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int enetc_open(struct net_device *ndev)
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int enetc_open(struct net_device *ndev)
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{
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{
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@ -2487,6 +2512,7 @@ err_phy_connect:
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return err;
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return err;
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}
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}
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EXPORT_SYMBOL_GPL(enetc_open);
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void enetc_stop(struct net_device *ndev)
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void enetc_stop(struct net_device *ndev)
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{
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{
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@ -2510,6 +2536,7 @@ void enetc_stop(struct net_device *ndev)
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|
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enetc_clear_interrupts(priv);
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enetc_clear_interrupts(priv);
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}
|
}
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EXPORT_SYMBOL_GPL(enetc_stop);
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|
|
||||||
int enetc_close(struct net_device *ndev)
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int enetc_close(struct net_device *ndev)
|
||||||
{
|
{
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|
@ -2534,6 +2561,7 @@ int enetc_close(struct net_device *ndev)
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||||||
|
|
||||||
return 0;
|
return 0;
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}
|
}
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EXPORT_SYMBOL_GPL(enetc_close);
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||||||
|
|
||||||
static int enetc_reconfigure(struct enetc_ndev_priv *priv, bool extended,
|
static int enetc_reconfigure(struct enetc_ndev_priv *priv, bool extended,
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int (*cb)(struct enetc_ndev_priv *priv, void *ctx),
|
int (*cb)(struct enetc_ndev_priv *priv, void *ctx),
|
||||||
|
@ -2642,6 +2670,7 @@ int enetc_setup_tc_mqprio(struct net_device *ndev, void *type_data)
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
EXPORT_SYMBOL_GPL(enetc_setup_tc_mqprio);
|
||||||
|
|
||||||
static int enetc_reconfigure_xdp_cb(struct enetc_ndev_priv *priv, void *ctx)
|
static int enetc_reconfigure_xdp_cb(struct enetc_ndev_priv *priv, void *ctx)
|
||||||
{
|
{
|
||||||
|
@ -2691,6 +2720,7 @@ int enetc_setup_bpf(struct net_device *ndev, struct netdev_bpf *bpf)
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
EXPORT_SYMBOL_GPL(enetc_setup_bpf);
|
||||||
|
|
||||||
struct net_device_stats *enetc_get_stats(struct net_device *ndev)
|
struct net_device_stats *enetc_get_stats(struct net_device *ndev)
|
||||||
{
|
{
|
||||||
|
@ -2722,6 +2752,7 @@ struct net_device_stats *enetc_get_stats(struct net_device *ndev)
|
||||||
|
|
||||||
return stats;
|
return stats;
|
||||||
}
|
}
|
||||||
|
EXPORT_SYMBOL_GPL(enetc_get_stats);
|
||||||
|
|
||||||
static int enetc_set_rss(struct net_device *ndev, int en)
|
static int enetc_set_rss(struct net_device *ndev, int en)
|
||||||
{
|
{
|
||||||
|
@ -2774,6 +2805,7 @@ void enetc_set_features(struct net_device *ndev, netdev_features_t features)
|
||||||
enetc_enable_txvlan(ndev,
|
enetc_enable_txvlan(ndev,
|
||||||
!!(features & NETIF_F_HW_VLAN_CTAG_TX));
|
!!(features & NETIF_F_HW_VLAN_CTAG_TX));
|
||||||
}
|
}
|
||||||
|
EXPORT_SYMBOL_GPL(enetc_set_features);
|
||||||
|
|
||||||
#ifdef CONFIG_FSL_ENETC_PTP_CLOCK
|
#ifdef CONFIG_FSL_ENETC_PTP_CLOCK
|
||||||
static int enetc_hwtstamp_set(struct net_device *ndev, struct ifreq *ifr)
|
static int enetc_hwtstamp_set(struct net_device *ndev, struct ifreq *ifr)
|
||||||
|
@ -2861,6 +2893,7 @@ int enetc_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
|
||||||
|
|
||||||
return phylink_mii_ioctl(priv->phylink, rq, cmd);
|
return phylink_mii_ioctl(priv->phylink, rq, cmd);
|
||||||
}
|
}
|
||||||
|
EXPORT_SYMBOL_GPL(enetc_ioctl);
|
||||||
|
|
||||||
int enetc_alloc_msix(struct enetc_ndev_priv *priv)
|
int enetc_alloc_msix(struct enetc_ndev_priv *priv)
|
||||||
{
|
{
|
||||||
|
@ -2962,6 +2995,7 @@ fail:
|
||||||
|
|
||||||
return err;
|
return err;
|
||||||
}
|
}
|
||||||
|
EXPORT_SYMBOL_GPL(enetc_alloc_msix);
|
||||||
|
|
||||||
void enetc_free_msix(struct enetc_ndev_priv *priv)
|
void enetc_free_msix(struct enetc_ndev_priv *priv)
|
||||||
{
|
{
|
||||||
|
@ -2991,6 +3025,7 @@ void enetc_free_msix(struct enetc_ndev_priv *priv)
|
||||||
/* disable all MSIX for this device */
|
/* disable all MSIX for this device */
|
||||||
pci_free_irq_vectors(priv->si->pdev);
|
pci_free_irq_vectors(priv->si->pdev);
|
||||||
}
|
}
|
||||||
|
EXPORT_SYMBOL_GPL(enetc_free_msix);
|
||||||
|
|
||||||
static void enetc_kfree_si(struct enetc_si *si)
|
static void enetc_kfree_si(struct enetc_si *si)
|
||||||
{
|
{
|
||||||
|
@ -3080,6 +3115,7 @@ err_dma:
|
||||||
|
|
||||||
return err;
|
return err;
|
||||||
}
|
}
|
||||||
|
EXPORT_SYMBOL_GPL(enetc_pci_probe);
|
||||||
|
|
||||||
void enetc_pci_remove(struct pci_dev *pdev)
|
void enetc_pci_remove(struct pci_dev *pdev)
|
||||||
{
|
{
|
||||||
|
@ -3091,3 +3127,6 @@ void enetc_pci_remove(struct pci_dev *pdev)
|
||||||
pci_release_mem_regions(pdev);
|
pci_release_mem_regions(pdev);
|
||||||
pci_disable_device(pdev);
|
pci_disable_device(pdev);
|
||||||
}
|
}
|
||||||
|
EXPORT_SYMBOL_GPL(enetc_pci_remove);
|
||||||
|
|
||||||
|
MODULE_LICENSE("Dual BSD/GPL");
|
||||||
|
|
|
@ -229,8 +229,9 @@ enum enetc_errata {
|
||||||
ENETC_ERR_UCMCSWP = BIT(1),
|
ENETC_ERR_UCMCSWP = BIT(1),
|
||||||
};
|
};
|
||||||
|
|
||||||
#define ENETC_SI_F_QBV BIT(0)
|
#define ENETC_SI_F_PSFP BIT(0)
|
||||||
#define ENETC_SI_F_PSFP BIT(1)
|
#define ENETC_SI_F_QBV BIT(1)
|
||||||
|
#define ENETC_SI_F_QBU BIT(2)
|
||||||
|
|
||||||
/* PCI IEP device data */
|
/* PCI IEP device data */
|
||||||
struct enetc_si {
|
struct enetc_si {
|
||||||
|
@ -396,6 +397,8 @@ struct enetc_msg_cmd_set_primary_mac {
|
||||||
extern int enetc_phc_index;
|
extern int enetc_phc_index;
|
||||||
|
|
||||||
/* SI common */
|
/* SI common */
|
||||||
|
u32 enetc_port_mac_rd(struct enetc_si *si, u32 reg);
|
||||||
|
void enetc_port_mac_wr(struct enetc_si *si, u32 reg, u32 val);
|
||||||
int enetc_pci_probe(struct pci_dev *pdev, const char *name, int sizeof_priv);
|
int enetc_pci_probe(struct pci_dev *pdev, const char *name, int sizeof_priv);
|
||||||
void enetc_pci_remove(struct pci_dev *pdev);
|
void enetc_pci_remove(struct pci_dev *pdev);
|
||||||
int enetc_alloc_msix(struct enetc_ndev_priv *priv);
|
int enetc_alloc_msix(struct enetc_ndev_priv *priv);
|
||||||
|
|
|
@ -44,6 +44,7 @@ int enetc_setup_cbdr(struct device *dev, struct enetc_hw *hw, int bd_count,
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
EXPORT_SYMBOL_GPL(enetc_setup_cbdr);
|
||||||
|
|
||||||
void enetc_teardown_cbdr(struct enetc_cbdr *cbdr)
|
void enetc_teardown_cbdr(struct enetc_cbdr *cbdr)
|
||||||
{
|
{
|
||||||
|
@ -57,6 +58,7 @@ void enetc_teardown_cbdr(struct enetc_cbdr *cbdr)
|
||||||
cbdr->bd_base = NULL;
|
cbdr->bd_base = NULL;
|
||||||
cbdr->dma_dev = NULL;
|
cbdr->dma_dev = NULL;
|
||||||
}
|
}
|
||||||
|
EXPORT_SYMBOL_GPL(enetc_teardown_cbdr);
|
||||||
|
|
||||||
static void enetc_clean_cbdr(struct enetc_cbdr *ring)
|
static void enetc_clean_cbdr(struct enetc_cbdr *ring)
|
||||||
{
|
{
|
||||||
|
@ -127,6 +129,7 @@ int enetc_send_cmd(struct enetc_si *si, struct enetc_cbd *cbd)
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
EXPORT_SYMBOL_GPL(enetc_send_cmd);
|
||||||
|
|
||||||
int enetc_clear_mac_flt_entry(struct enetc_si *si, int index)
|
int enetc_clear_mac_flt_entry(struct enetc_si *si, int index)
|
||||||
{
|
{
|
||||||
|
@ -140,6 +143,7 @@ int enetc_clear_mac_flt_entry(struct enetc_si *si, int index)
|
||||||
|
|
||||||
return enetc_send_cmd(si, &cbd);
|
return enetc_send_cmd(si, &cbd);
|
||||||
}
|
}
|
||||||
|
EXPORT_SYMBOL_GPL(enetc_clear_mac_flt_entry);
|
||||||
|
|
||||||
int enetc_set_mac_flt_entry(struct enetc_si *si, int index,
|
int enetc_set_mac_flt_entry(struct enetc_si *si, int index,
|
||||||
char *mac_addr, int si_map)
|
char *mac_addr, int si_map)
|
||||||
|
@ -165,6 +169,7 @@ int enetc_set_mac_flt_entry(struct enetc_si *si, int index,
|
||||||
|
|
||||||
return enetc_send_cmd(si, &cbd);
|
return enetc_send_cmd(si, &cbd);
|
||||||
}
|
}
|
||||||
|
EXPORT_SYMBOL_GPL(enetc_set_mac_flt_entry);
|
||||||
|
|
||||||
/* Set entry in RFS table */
|
/* Set entry in RFS table */
|
||||||
int enetc_set_fs_entry(struct enetc_si *si, struct enetc_cmd_rfse *rfse,
|
int enetc_set_fs_entry(struct enetc_si *si, struct enetc_cmd_rfse *rfse,
|
||||||
|
@ -197,6 +202,7 @@ int enetc_set_fs_entry(struct enetc_si *si, struct enetc_cmd_rfse *rfse,
|
||||||
|
|
||||||
return err;
|
return err;
|
||||||
}
|
}
|
||||||
|
EXPORT_SYMBOL_GPL(enetc_set_fs_entry);
|
||||||
|
|
||||||
static int enetc_cmd_rss_table(struct enetc_si *si, u32 *table, int count,
|
static int enetc_cmd_rss_table(struct enetc_si *si, u32 *table, int count,
|
||||||
bool read)
|
bool read)
|
||||||
|
@ -242,9 +248,11 @@ int enetc_get_rss_table(struct enetc_si *si, u32 *table, int count)
|
||||||
{
|
{
|
||||||
return enetc_cmd_rss_table(si, table, count, true);
|
return enetc_cmd_rss_table(si, table, count, true);
|
||||||
}
|
}
|
||||||
|
EXPORT_SYMBOL_GPL(enetc_get_rss_table);
|
||||||
|
|
||||||
/* Set RSS table */
|
/* Set RSS table */
|
||||||
int enetc_set_rss_table(struct enetc_si *si, const u32 *table, int count)
|
int enetc_set_rss_table(struct enetc_si *si, const u32 *table, int count)
|
||||||
{
|
{
|
||||||
return enetc_cmd_rss_table(si, (u32 *)table, count, false);
|
return enetc_cmd_rss_table(si, (u32 *)table, count, false);
|
||||||
}
|
}
|
||||||
|
EXPORT_SYMBOL_GPL(enetc_set_rss_table);
|
||||||
|
|
|
@ -649,6 +649,7 @@ void enetc_set_rss_key(struct enetc_hw *hw, const u8 *bytes)
|
||||||
for (i = 0; i < ENETC_RSSHASH_KEY_SIZE / 4; i++)
|
for (i = 0; i < ENETC_RSSHASH_KEY_SIZE / 4; i++)
|
||||||
enetc_port_wr(hw, ENETC_PRSSK(i), ((u32 *)bytes)[i]);
|
enetc_port_wr(hw, ENETC_PRSSK(i), ((u32 *)bytes)[i]);
|
||||||
}
|
}
|
||||||
|
EXPORT_SYMBOL_GPL(enetc_set_rss_key);
|
||||||
|
|
||||||
static int enetc_set_rxfh(struct net_device *ndev, const u32 *indir,
|
static int enetc_set_rxfh(struct net_device *ndev, const u32 *indir,
|
||||||
const u8 *key, const u8 hfunc)
|
const u8 *key, const u8 hfunc)
|
||||||
|
@ -924,3 +925,4 @@ void enetc_set_ethtool_ops(struct net_device *ndev)
|
||||||
else
|
else
|
||||||
ndev->ethtool_ops = &enetc_vf_ethtool_ops;
|
ndev->ethtool_ops = &enetc_vf_ethtool_ops;
|
||||||
}
|
}
|
||||||
|
EXPORT_SYMBOL_GPL(enetc_set_ethtool_ops);
|
||||||
|
|
|
@ -18,9 +18,10 @@
|
||||||
#define ENETC_SICTR0 0x18
|
#define ENETC_SICTR0 0x18
|
||||||
#define ENETC_SICTR1 0x1c
|
#define ENETC_SICTR1 0x1c
|
||||||
#define ENETC_SIPCAPR0 0x20
|
#define ENETC_SIPCAPR0 0x20
|
||||||
#define ENETC_SIPCAPR0_QBV BIT(4)
|
|
||||||
#define ENETC_SIPCAPR0_PSFP BIT(9)
|
#define ENETC_SIPCAPR0_PSFP BIT(9)
|
||||||
#define ENETC_SIPCAPR0_RSS BIT(8)
|
#define ENETC_SIPCAPR0_RSS BIT(8)
|
||||||
|
#define ENETC_SIPCAPR0_QBV BIT(4)
|
||||||
|
#define ENETC_SIPCAPR0_QBU BIT(3)
|
||||||
#define ENETC_SIPCAPR1 0x24
|
#define ENETC_SIPCAPR1 0x24
|
||||||
#define ENETC_SITGTGR 0x30
|
#define ENETC_SITGTGR 0x30
|
||||||
#define ENETC_SIRBGCR 0x38
|
#define ENETC_SIRBGCR 0x38
|
||||||
|
@ -213,7 +214,6 @@ enum enetc_bdr_type {TX, RX};
|
||||||
#define ENETC_PSIRFSCFGR(n) (0x1814 + (n) * 4) /* n = SI index */
|
#define ENETC_PSIRFSCFGR(n) (0x1814 + (n) * 4) /* n = SI index */
|
||||||
#define ENETC_PFPMR 0x1900
|
#define ENETC_PFPMR 0x1900
|
||||||
#define ENETC_PFPMR_PMACE BIT(1)
|
#define ENETC_PFPMR_PMACE BIT(1)
|
||||||
#define ENETC_PFPMR_MWLM BIT(0)
|
|
||||||
#define ENETC_EMDIO_BASE 0x1c00
|
#define ENETC_EMDIO_BASE 0x1c00
|
||||||
#define ENETC_PSIUMHFR0(n, err) (((err) ? 0x1d08 : 0x1d00) + (n) * 0x10)
|
#define ENETC_PSIUMHFR0(n, err) (((err) ? 0x1d08 : 0x1d00) + (n) * 0x10)
|
||||||
#define ENETC_PSIUMHFR1(n) (0x1d04 + (n) * 0x10)
|
#define ENETC_PSIUMHFR1(n) (0x1d04 + (n) * 0x10)
|
||||||
|
@ -225,8 +225,9 @@ enum enetc_bdr_type {TX, RX};
|
||||||
#define ENETC_MMCSR_ME BIT(16)
|
#define ENETC_MMCSR_ME BIT(16)
|
||||||
#define ENETC_PTCMSDUR(n) (0x2020 + (n) * 4) /* n = TC index [0..7] */
|
#define ENETC_PTCMSDUR(n) (0x2020 + (n) * 4) /* n = TC index [0..7] */
|
||||||
|
|
||||||
|
#define ENETC_PMAC_OFFSET 0x1000
|
||||||
|
|
||||||
#define ENETC_PM0_CMD_CFG 0x8008
|
#define ENETC_PM0_CMD_CFG 0x8008
|
||||||
#define ENETC_PM1_CMD_CFG 0x9008
|
|
||||||
#define ENETC_PM0_TX_EN BIT(0)
|
#define ENETC_PM0_TX_EN BIT(0)
|
||||||
#define ENETC_PM0_RX_EN BIT(1)
|
#define ENETC_PM0_RX_EN BIT(1)
|
||||||
#define ENETC_PM0_PROMISC BIT(4)
|
#define ENETC_PM0_PROMISC BIT(4)
|
||||||
|
@ -245,11 +246,8 @@ enum enetc_bdr_type {TX, RX};
|
||||||
|
|
||||||
#define ENETC_PM0_PAUSE_QUANTA 0x8054
|
#define ENETC_PM0_PAUSE_QUANTA 0x8054
|
||||||
#define ENETC_PM0_PAUSE_THRESH 0x8064
|
#define ENETC_PM0_PAUSE_THRESH 0x8064
|
||||||
#define ENETC_PM1_PAUSE_QUANTA 0x9054
|
|
||||||
#define ENETC_PM1_PAUSE_THRESH 0x9064
|
|
||||||
|
|
||||||
#define ENETC_PM0_SINGLE_STEP 0x80c0
|
#define ENETC_PM0_SINGLE_STEP 0x80c0
|
||||||
#define ENETC_PM1_SINGLE_STEP 0x90c0
|
|
||||||
#define ENETC_PM0_SINGLE_STEP_CH BIT(7)
|
#define ENETC_PM0_SINGLE_STEP_CH BIT(7)
|
||||||
#define ENETC_PM0_SINGLE_STEP_EN BIT(31)
|
#define ENETC_PM0_SINGLE_STEP_EN BIT(31)
|
||||||
#define ENETC_SET_SINGLE_STEP_OFFSET(v) (((v) & 0xff) << 8)
|
#define ENETC_SET_SINGLE_STEP_OFFSET(v) (((v) & 0xff) << 8)
|
||||||
|
@ -279,57 +277,57 @@ enum enetc_bdr_type {TX, RX};
|
||||||
/* Port MAC counters: Port MAC 0 corresponds to the eMAC and
|
/* Port MAC counters: Port MAC 0 corresponds to the eMAC and
|
||||||
* Port MAC 1 to the pMAC.
|
* Port MAC 1 to the pMAC.
|
||||||
*/
|
*/
|
||||||
#define ENETC_PM_REOCT(mac) (0x8100 + 0x1000 * (mac))
|
#define ENETC_PM_REOCT(mac) (0x8100 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_RALN(mac) (0x8110 + 0x1000 * (mac))
|
#define ENETC_PM_RALN(mac) (0x8110 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_RXPF(mac) (0x8118 + 0x1000 * (mac))
|
#define ENETC_PM_RXPF(mac) (0x8118 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_RFRM(mac) (0x8120 + 0x1000 * (mac))
|
#define ENETC_PM_RFRM(mac) (0x8120 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_RFCS(mac) (0x8128 + 0x1000 * (mac))
|
#define ENETC_PM_RFCS(mac) (0x8128 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_RVLAN(mac) (0x8130 + 0x1000 * (mac))
|
#define ENETC_PM_RVLAN(mac) (0x8130 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_RERR(mac) (0x8138 + 0x1000 * (mac))
|
#define ENETC_PM_RERR(mac) (0x8138 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_RUCA(mac) (0x8140 + 0x1000 * (mac))
|
#define ENETC_PM_RUCA(mac) (0x8140 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_RMCA(mac) (0x8148 + 0x1000 * (mac))
|
#define ENETC_PM_RMCA(mac) (0x8148 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_RBCA(mac) (0x8150 + 0x1000 * (mac))
|
#define ENETC_PM_RBCA(mac) (0x8150 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_RDRP(mac) (0x8158 + 0x1000 * (mac))
|
#define ENETC_PM_RDRP(mac) (0x8158 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_RPKT(mac) (0x8160 + 0x1000 * (mac))
|
#define ENETC_PM_RPKT(mac) (0x8160 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_RUND(mac) (0x8168 + 0x1000 * (mac))
|
#define ENETC_PM_RUND(mac) (0x8168 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_R64(mac) (0x8170 + 0x1000 * (mac))
|
#define ENETC_PM_R64(mac) (0x8170 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_R127(mac) (0x8178 + 0x1000 * (mac))
|
#define ENETC_PM_R127(mac) (0x8178 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_R255(mac) (0x8180 + 0x1000 * (mac))
|
#define ENETC_PM_R255(mac) (0x8180 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_R511(mac) (0x8188 + 0x1000 * (mac))
|
#define ENETC_PM_R511(mac) (0x8188 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_R1023(mac) (0x8190 + 0x1000 * (mac))
|
#define ENETC_PM_R1023(mac) (0x8190 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_R1522(mac) (0x8198 + 0x1000 * (mac))
|
#define ENETC_PM_R1522(mac) (0x8198 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_R1523X(mac) (0x81A0 + 0x1000 * (mac))
|
#define ENETC_PM_R1523X(mac) (0x81A0 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_ROVR(mac) (0x81A8 + 0x1000 * (mac))
|
#define ENETC_PM_ROVR(mac) (0x81A8 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_RJBR(mac) (0x81B0 + 0x1000 * (mac))
|
#define ENETC_PM_RJBR(mac) (0x81B0 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_RFRG(mac) (0x81B8 + 0x1000 * (mac))
|
#define ENETC_PM_RFRG(mac) (0x81B8 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_RCNP(mac) (0x81C0 + 0x1000 * (mac))
|
#define ENETC_PM_RCNP(mac) (0x81C0 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_RDRNTP(mac) (0x81C8 + 0x1000 * (mac))
|
#define ENETC_PM_RDRNTP(mac) (0x81C8 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_TEOCT(mac) (0x8200 + 0x1000 * (mac))
|
#define ENETC_PM_TEOCT(mac) (0x8200 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_TOCT(mac) (0x8208 + 0x1000 * (mac))
|
#define ENETC_PM_TOCT(mac) (0x8208 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_TCRSE(mac) (0x8210 + 0x1000 * (mac))
|
#define ENETC_PM_TCRSE(mac) (0x8210 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_TXPF(mac) (0x8218 + 0x1000 * (mac))
|
#define ENETC_PM_TXPF(mac) (0x8218 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_TFRM(mac) (0x8220 + 0x1000 * (mac))
|
#define ENETC_PM_TFRM(mac) (0x8220 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_TFCS(mac) (0x8228 + 0x1000 * (mac))
|
#define ENETC_PM_TFCS(mac) (0x8228 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_TVLAN(mac) (0x8230 + 0x1000 * (mac))
|
#define ENETC_PM_TVLAN(mac) (0x8230 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_TERR(mac) (0x8238 + 0x1000 * (mac))
|
#define ENETC_PM_TERR(mac) (0x8238 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_TUCA(mac) (0x8240 + 0x1000 * (mac))
|
#define ENETC_PM_TUCA(mac) (0x8240 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_TMCA(mac) (0x8248 + 0x1000 * (mac))
|
#define ENETC_PM_TMCA(mac) (0x8248 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_TBCA(mac) (0x8250 + 0x1000 * (mac))
|
#define ENETC_PM_TBCA(mac) (0x8250 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_TPKT(mac) (0x8260 + 0x1000 * (mac))
|
#define ENETC_PM_TPKT(mac) (0x8260 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_TUND(mac) (0x8268 + 0x1000 * (mac))
|
#define ENETC_PM_TUND(mac) (0x8268 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_T64(mac) (0x8270 + 0x1000 * (mac))
|
#define ENETC_PM_T64(mac) (0x8270 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_T127(mac) (0x8278 + 0x1000 * (mac))
|
#define ENETC_PM_T127(mac) (0x8278 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_T255(mac) (0x8280 + 0x1000 * (mac))
|
#define ENETC_PM_T255(mac) (0x8280 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_T511(mac) (0x8288 + 0x1000 * (mac))
|
#define ENETC_PM_T511(mac) (0x8288 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_T1023(mac) (0x8290 + 0x1000 * (mac))
|
#define ENETC_PM_T1023(mac) (0x8290 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_T1522(mac) (0x8298 + 0x1000 * (mac))
|
#define ENETC_PM_T1522(mac) (0x8298 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_T1523X(mac) (0x82A0 + 0x1000 * (mac))
|
#define ENETC_PM_T1523X(mac) (0x82A0 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_TCNP(mac) (0x82C0 + 0x1000 * (mac))
|
#define ENETC_PM_TCNP(mac) (0x82C0 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_TDFR(mac) (0x82D0 + 0x1000 * (mac))
|
#define ENETC_PM_TDFR(mac) (0x82D0 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_TMCOL(mac) (0x82D8 + 0x1000 * (mac))
|
#define ENETC_PM_TMCOL(mac) (0x82D8 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_TSCOL(mac) (0x82E0 + 0x1000 * (mac))
|
#define ENETC_PM_TSCOL(mac) (0x82E0 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_TLCOL(mac) (0x82E8 + 0x1000 * (mac))
|
#define ENETC_PM_TLCOL(mac) (0x82E8 + ENETC_PMAC_OFFSET * (mac))
|
||||||
#define ENETC_PM_TECOL(mac) (0x82F0 + 0x1000 * (mac))
|
#define ENETC_PM_TECOL(mac) (0x82F0 + ENETC_PMAC_OFFSET * (mac))
|
||||||
|
|
||||||
/* Port counters */
|
/* Port counters */
|
||||||
#define ENETC_PICDR(n) (0x0700 + (n) * 8) /* n = [0..3] */
|
#define ENETC_PICDR(n) (0x0700 + (n) * 8) /* n = [0..3] */
|
||||||
|
|
|
@ -319,24 +319,23 @@ static int enetc_vlan_rx_del_vid(struct net_device *ndev, __be16 prot, u16 vid)
|
||||||
static void enetc_set_loopback(struct net_device *ndev, bool en)
|
static void enetc_set_loopback(struct net_device *ndev, bool en)
|
||||||
{
|
{
|
||||||
struct enetc_ndev_priv *priv = netdev_priv(ndev);
|
struct enetc_ndev_priv *priv = netdev_priv(ndev);
|
||||||
struct enetc_hw *hw = &priv->si->hw;
|
struct enetc_si *si = priv->si;
|
||||||
u32 reg;
|
u32 reg;
|
||||||
|
|
||||||
reg = enetc_port_rd(hw, ENETC_PM0_IF_MODE);
|
reg = enetc_port_mac_rd(si, ENETC_PM0_IF_MODE);
|
||||||
if (reg & ENETC_PM0_IFM_RG) {
|
if (reg & ENETC_PM0_IFM_RG) {
|
||||||
/* RGMII mode */
|
/* RGMII mode */
|
||||||
reg = (reg & ~ENETC_PM0_IFM_RLP) |
|
reg = (reg & ~ENETC_PM0_IFM_RLP) |
|
||||||
(en ? ENETC_PM0_IFM_RLP : 0);
|
(en ? ENETC_PM0_IFM_RLP : 0);
|
||||||
enetc_port_wr(hw, ENETC_PM0_IF_MODE, reg);
|
enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, reg);
|
||||||
} else {
|
} else {
|
||||||
/* assume SGMII mode */
|
/* assume SGMII mode */
|
||||||
reg = enetc_port_rd(hw, ENETC_PM0_CMD_CFG);
|
reg = enetc_port_mac_rd(si, ENETC_PM0_CMD_CFG);
|
||||||
reg = (reg & ~ENETC_PM0_CMD_XGLP) |
|
reg = (reg & ~ENETC_PM0_CMD_XGLP) |
|
||||||
(en ? ENETC_PM0_CMD_XGLP : 0);
|
(en ? ENETC_PM0_CMD_XGLP : 0);
|
||||||
reg = (reg & ~ENETC_PM0_CMD_PHY_TX_EN) |
|
reg = (reg & ~ENETC_PM0_CMD_PHY_TX_EN) |
|
||||||
(en ? ENETC_PM0_CMD_PHY_TX_EN : 0);
|
(en ? ENETC_PM0_CMD_PHY_TX_EN : 0);
|
||||||
enetc_port_wr(hw, ENETC_PM0_CMD_CFG, reg);
|
enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, reg);
|
||||||
enetc_port_wr(hw, ENETC_PM1_CMD_CFG, reg);
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -538,65 +537,50 @@ void enetc_reset_ptcmsdur(struct enetc_hw *hw)
|
||||||
enetc_port_wr(hw, ENETC_PTCMSDUR(tc), ENETC_MAC_MAXFRM_SIZE);
|
enetc_port_wr(hw, ENETC_PTCMSDUR(tc), ENETC_MAC_MAXFRM_SIZE);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void enetc_configure_port_mac(struct enetc_hw *hw)
|
static void enetc_configure_port_mac(struct enetc_si *si)
|
||||||
{
|
{
|
||||||
enetc_port_wr(hw, ENETC_PM0_MAXFRM,
|
struct enetc_hw *hw = &si->hw;
|
||||||
|
|
||||||
|
enetc_port_mac_wr(si, ENETC_PM0_MAXFRM,
|
||||||
ENETC_SET_MAXFRM(ENETC_RX_MAXFRM_SIZE));
|
ENETC_SET_MAXFRM(ENETC_RX_MAXFRM_SIZE));
|
||||||
|
|
||||||
enetc_reset_ptcmsdur(hw);
|
enetc_reset_ptcmsdur(hw);
|
||||||
|
|
||||||
enetc_port_wr(hw, ENETC_PM0_CMD_CFG, ENETC_PM0_CMD_PHY_TX_EN |
|
enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, ENETC_PM0_CMD_PHY_TX_EN |
|
||||||
ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC);
|
|
||||||
|
|
||||||
enetc_port_wr(hw, ENETC_PM1_CMD_CFG, ENETC_PM0_CMD_PHY_TX_EN |
|
|
||||||
ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC);
|
ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC);
|
||||||
|
|
||||||
/* On LS1028A, the MAC RX FIFO defaults to 2, which is too high
|
/* On LS1028A, the MAC RX FIFO defaults to 2, which is too high
|
||||||
* and may lead to RX lock-up under traffic. Set it to 1 instead,
|
* and may lead to RX lock-up under traffic. Set it to 1 instead,
|
||||||
* as recommended by the hardware team.
|
* as recommended by the hardware team.
|
||||||
*/
|
*/
|
||||||
enetc_port_wr(hw, ENETC_PM0_RX_FIFO, ENETC_PM0_RX_FIFO_VAL);
|
enetc_port_mac_wr(si, ENETC_PM0_RX_FIFO, ENETC_PM0_RX_FIFO_VAL);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void enetc_mac_config(struct enetc_hw *hw, phy_interface_t phy_mode)
|
static void enetc_mac_config(struct enetc_si *si, phy_interface_t phy_mode)
|
||||||
{
|
{
|
||||||
u32 val;
|
u32 val;
|
||||||
|
|
||||||
if (phy_interface_mode_is_rgmii(phy_mode)) {
|
if (phy_interface_mode_is_rgmii(phy_mode)) {
|
||||||
val = enetc_port_rd(hw, ENETC_PM0_IF_MODE);
|
val = enetc_port_mac_rd(si, ENETC_PM0_IF_MODE);
|
||||||
val &= ~(ENETC_PM0_IFM_EN_AUTO | ENETC_PM0_IFM_IFMODE_MASK);
|
val &= ~(ENETC_PM0_IFM_EN_AUTO | ENETC_PM0_IFM_IFMODE_MASK);
|
||||||
val |= ENETC_PM0_IFM_IFMODE_GMII | ENETC_PM0_IFM_RG;
|
val |= ENETC_PM0_IFM_IFMODE_GMII | ENETC_PM0_IFM_RG;
|
||||||
enetc_port_wr(hw, ENETC_PM0_IF_MODE, val);
|
enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, val);
|
||||||
}
|
}
|
||||||
|
|
||||||
if (phy_mode == PHY_INTERFACE_MODE_USXGMII) {
|
if (phy_mode == PHY_INTERFACE_MODE_USXGMII) {
|
||||||
val = ENETC_PM0_IFM_FULL_DPX | ENETC_PM0_IFM_IFMODE_XGMII;
|
val = ENETC_PM0_IFM_FULL_DPX | ENETC_PM0_IFM_IFMODE_XGMII;
|
||||||
enetc_port_wr(hw, ENETC_PM0_IF_MODE, val);
|
enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, val);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static void enetc_mac_enable(struct enetc_hw *hw, bool en)
|
static void enetc_mac_enable(struct enetc_si *si, bool en)
|
||||||
{
|
{
|
||||||
u32 val = enetc_port_rd(hw, ENETC_PM0_CMD_CFG);
|
u32 val = enetc_port_mac_rd(si, ENETC_PM0_CMD_CFG);
|
||||||
|
|
||||||
val &= ~(ENETC_PM0_TX_EN | ENETC_PM0_RX_EN);
|
val &= ~(ENETC_PM0_TX_EN | ENETC_PM0_RX_EN);
|
||||||
val |= en ? (ENETC_PM0_TX_EN | ENETC_PM0_RX_EN) : 0;
|
val |= en ? (ENETC_PM0_TX_EN | ENETC_PM0_RX_EN) : 0;
|
||||||
|
|
||||||
enetc_port_wr(hw, ENETC_PM0_CMD_CFG, val);
|
enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, val);
|
||||||
enetc_port_wr(hw, ENETC_PM1_CMD_CFG, val);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void enetc_configure_port_pmac(struct enetc_hw *hw)
|
|
||||||
{
|
|
||||||
u32 temp;
|
|
||||||
|
|
||||||
/* Set pMAC step lock */
|
|
||||||
temp = enetc_port_rd(hw, ENETC_PFPMR);
|
|
||||||
enetc_port_wr(hw, ENETC_PFPMR,
|
|
||||||
temp | ENETC_PFPMR_PMACE | ENETC_PFPMR_MWLM);
|
|
||||||
|
|
||||||
temp = enetc_port_rd(hw, ENETC_MMCSR);
|
|
||||||
enetc_port_wr(hw, ENETC_MMCSR, temp | ENETC_MMCSR_ME);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static void enetc_configure_port(struct enetc_pf *pf)
|
static void enetc_configure_port(struct enetc_pf *pf)
|
||||||
|
@ -604,9 +588,7 @@ static void enetc_configure_port(struct enetc_pf *pf)
|
||||||
u8 hash_key[ENETC_RSSHASH_KEY_SIZE];
|
u8 hash_key[ENETC_RSSHASH_KEY_SIZE];
|
||||||
struct enetc_hw *hw = &pf->si->hw;
|
struct enetc_hw *hw = &pf->si->hw;
|
||||||
|
|
||||||
enetc_configure_port_pmac(hw);
|
enetc_configure_port_mac(pf->si);
|
||||||
|
|
||||||
enetc_configure_port_mac(hw);
|
|
||||||
|
|
||||||
enetc_port_si_configure(pf->si);
|
enetc_port_si_configure(pf->si);
|
||||||
|
|
||||||
|
@ -998,14 +980,14 @@ static void enetc_pl_mac_config(struct phylink_config *config,
|
||||||
{
|
{
|
||||||
struct enetc_pf *pf = phylink_to_enetc_pf(config);
|
struct enetc_pf *pf = phylink_to_enetc_pf(config);
|
||||||
|
|
||||||
enetc_mac_config(&pf->si->hw, state->interface);
|
enetc_mac_config(pf->si, state->interface);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void enetc_force_rgmii_mac(struct enetc_hw *hw, int speed, int duplex)
|
static void enetc_force_rgmii_mac(struct enetc_si *si, int speed, int duplex)
|
||||||
{
|
{
|
||||||
u32 old_val, val;
|
u32 old_val, val;
|
||||||
|
|
||||||
old_val = val = enetc_port_rd(hw, ENETC_PM0_IF_MODE);
|
old_val = val = enetc_port_mac_rd(si, ENETC_PM0_IF_MODE);
|
||||||
|
|
||||||
if (speed == SPEED_1000) {
|
if (speed == SPEED_1000) {
|
||||||
val &= ~ENETC_PM0_IFM_SSP_MASK;
|
val &= ~ENETC_PM0_IFM_SSP_MASK;
|
||||||
|
@ -1026,7 +1008,7 @@ static void enetc_force_rgmii_mac(struct enetc_hw *hw, int speed, int duplex)
|
||||||
if (val == old_val)
|
if (val == old_val)
|
||||||
return;
|
return;
|
||||||
|
|
||||||
enetc_port_wr(hw, ENETC_PM0_IF_MODE, val);
|
enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, val);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void enetc_pl_mac_link_up(struct phylink_config *config,
|
static void enetc_pl_mac_link_up(struct phylink_config *config,
|
||||||
|
@ -1038,6 +1020,7 @@ static void enetc_pl_mac_link_up(struct phylink_config *config,
|
||||||
u32 pause_off_thresh = 0, pause_on_thresh = 0;
|
u32 pause_off_thresh = 0, pause_on_thresh = 0;
|
||||||
u32 init_quanta = 0, refresh_quanta = 0;
|
u32 init_quanta = 0, refresh_quanta = 0;
|
||||||
struct enetc_hw *hw = &pf->si->hw;
|
struct enetc_hw *hw = &pf->si->hw;
|
||||||
|
struct enetc_si *si = pf->si;
|
||||||
struct enetc_ndev_priv *priv;
|
struct enetc_ndev_priv *priv;
|
||||||
u32 rbmr, cmd_cfg;
|
u32 rbmr, cmd_cfg;
|
||||||
int idx;
|
int idx;
|
||||||
|
@ -1049,7 +1032,7 @@ static void enetc_pl_mac_link_up(struct phylink_config *config,
|
||||||
|
|
||||||
if (!phylink_autoneg_inband(mode) &&
|
if (!phylink_autoneg_inband(mode) &&
|
||||||
phy_interface_mode_is_rgmii(interface))
|
phy_interface_mode_is_rgmii(interface))
|
||||||
enetc_force_rgmii_mac(hw, speed, duplex);
|
enetc_force_rgmii_mac(si, speed, duplex);
|
||||||
|
|
||||||
/* Flow control */
|
/* Flow control */
|
||||||
for (idx = 0; idx < priv->num_rx_rings; idx++) {
|
for (idx = 0; idx < priv->num_rx_rings; idx++) {
|
||||||
|
@ -1085,24 +1068,21 @@ static void enetc_pl_mac_link_up(struct phylink_config *config,
|
||||||
pause_off_thresh = 1 * ENETC_MAC_MAXFRM_SIZE;
|
pause_off_thresh = 1 * ENETC_MAC_MAXFRM_SIZE;
|
||||||
}
|
}
|
||||||
|
|
||||||
enetc_port_wr(hw, ENETC_PM0_PAUSE_QUANTA, init_quanta);
|
enetc_port_mac_wr(si, ENETC_PM0_PAUSE_QUANTA, init_quanta);
|
||||||
enetc_port_wr(hw, ENETC_PM1_PAUSE_QUANTA, init_quanta);
|
enetc_port_mac_wr(si, ENETC_PM0_PAUSE_THRESH, refresh_quanta);
|
||||||
enetc_port_wr(hw, ENETC_PM0_PAUSE_THRESH, refresh_quanta);
|
|
||||||
enetc_port_wr(hw, ENETC_PM1_PAUSE_THRESH, refresh_quanta);
|
|
||||||
enetc_port_wr(hw, ENETC_PPAUONTR, pause_on_thresh);
|
enetc_port_wr(hw, ENETC_PPAUONTR, pause_on_thresh);
|
||||||
enetc_port_wr(hw, ENETC_PPAUOFFTR, pause_off_thresh);
|
enetc_port_wr(hw, ENETC_PPAUOFFTR, pause_off_thresh);
|
||||||
|
|
||||||
cmd_cfg = enetc_port_rd(hw, ENETC_PM0_CMD_CFG);
|
cmd_cfg = enetc_port_mac_rd(si, ENETC_PM0_CMD_CFG);
|
||||||
|
|
||||||
if (rx_pause)
|
if (rx_pause)
|
||||||
cmd_cfg &= ~ENETC_PM0_PAUSE_IGN;
|
cmd_cfg &= ~ENETC_PM0_PAUSE_IGN;
|
||||||
else
|
else
|
||||||
cmd_cfg |= ENETC_PM0_PAUSE_IGN;
|
cmd_cfg |= ENETC_PM0_PAUSE_IGN;
|
||||||
|
|
||||||
enetc_port_wr(hw, ENETC_PM0_CMD_CFG, cmd_cfg);
|
enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, cmd_cfg);
|
||||||
enetc_port_wr(hw, ENETC_PM1_CMD_CFG, cmd_cfg);
|
|
||||||
|
|
||||||
enetc_mac_enable(hw, true);
|
enetc_mac_enable(si, true);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void enetc_pl_mac_link_down(struct phylink_config *config,
|
static void enetc_pl_mac_link_down(struct phylink_config *config,
|
||||||
|
@ -1111,7 +1091,7 @@ static void enetc_pl_mac_link_down(struct phylink_config *config,
|
||||||
{
|
{
|
||||||
struct enetc_pf *pf = phylink_to_enetc_pf(config);
|
struct enetc_pf *pf = phylink_to_enetc_pf(config);
|
||||||
|
|
||||||
enetc_mac_enable(&pf->si->hw, false);
|
enetc_mac_enable(pf->si, false);
|
||||||
}
|
}
|
||||||
|
|
||||||
static const struct phylink_mac_ops enetc_mac_phylink_ops = {
|
static const struct phylink_mac_ops enetc_mac_phylink_ops = {
|
||||||
|
|
Loading…
Reference in New Issue