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alinux: arm64: adjust tk_core memory layout 

to #29722367

On some specific hardware with 128 bytes LLC cacheline, tk_core may
cause false sharing problem. We can align it to 128 bytes so that
it won't be affected by other global variables.

This change will make a bit waste on cache utilization but get good
number of performance improvement. So for both 64 and 128 bytes aligned
LLC cacheline, we adjust tk_core memory layout to avoid potential cacheline
contention.

Signed-off-by: Peng Wang <rocking@linux.alibaba.com>
Acked-by: Shanpei Chen <shanpeic@linux.alibaba.com>
Reviewed-by: Shile Zhang <shile.zhang@linux.alibaba.com>
Signed-off-by: caelli <caelli@tencent.com>
Reviewed-by: yilingjin <yilingjin@tencent.com>
Reviewed-by: yuehongwu <yuehongwu@tencent.com>
Signed-off-by: Jianping Liu <frankjpliu@tencent.com>
This commit is contained in:
caelli 2024-04-17 14:56:44 +08:00 committed by Jianping Liu
parent 9e1bfb392a
commit 7a94805aa8
3 changed files with 26 additions and 0 deletions
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10
arch/arm64/Kconfig
View File

@ -1101,6 +1101,16 @@ config ARCH_HAS_CACHE_LINE_SIZE
config ARCH_ENABLE_SPLIT_PMD_PTLOCK
def_bool y if PGTABLE_LEVELS > 2
config ARCH_LLC_128_WORKAROUND
bool "Workaround for 128 bytes LLC cacheline"
depends on ARM64
default n
help
LLC cacheline size may be up to 128 bytes, and this
is useful if you want to do workaround on such
case. It can be used to align memory address to get
good cache utilization et al.
config SECCOMP
bool "Enable seccomp to safely compute untrusted bytecode"
---help---

1
arch/arm64/configs/tencent.config
View File

@ -666,6 +666,7 @@ CONFIG_SCSI_AIC7XXX=m
CONFIG_SCSI_AIC79XX=m
CONFIG_AIC79XX_CMDS_PER_DEVICE=4
CONFIG_AIC79XX_RESET_DELAY_MS=15000
CONFIG_ARCH_LLC_128_WORKAROUND=y
# CONFIG_AIC79XX_DEBUG_ENABLE is not set
# CONFIG_AIC79XX_REG_PRETTY_PRINT is not set
CONFIG_SCSI_AIC94XX=m

15
kernel/time/timekeeping.c
View File

@ -46,9 +46,24 @@ enum timekeeping_adv_mode {
* cache line.
*/
static struct {
#ifdef CONFIG_ARCH_LLC_128_WORKAROUND
/* Start seq on the middle of 128 bytes aligned address to
* keep some members of tk_core in the same 64 bytes for
* principle of locality while pushing others to another LLC
* cacheline to avoid false sharing.
*/
u8 padding1[64];
seqcount_t seq;
/* Push some timekeeper memebers to another LLC cacheline */
u8 padding2[16];
struct timekeeper timekeeper;
/* For 128 bytes LLC cacheline */
} tk_core __aligned(128) = {
#else
seqcount_t seq;
struct timekeeper timekeeper;
} tk_core ____cacheline_aligned = {
#endif
.seq = SEQCNT_ZERO(tk_core.seq),
};