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ASoC: sun8i-codec: Generalize AIF clock control 

The AIF clock control register has the same layout for all three AIFs.
The only difference between them is that AIF3 is missing some fields. We
can reuse the same register field definitions for all three registers,
and use the DAI ID to select the correct register address.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Maxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20201014061941.4306-16-samuel@sholland.org
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Samuel Holland 2020-10-14 01:19:39 -05:00 committed by Mark Brown
parent 342cacb92d
commit 7a6b937ec4
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
1 changed files with 32 additions and 30 deletions
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62
sound/soc/sunxi/sun8i-codec.c
View File

@ -42,13 +42,13 @@
#define SUN8I_SYS_SR_CTRL 0x018
#define SUN8I_SYS_SR_CTRL_AIF1_FS 12
#define SUN8I_SYS_SR_CTRL_AIF2_FS 8
#define SUN8I_AIF1CLK_CTRL 0x040
#define SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD 15
#define SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV 13
#define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV 9
#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV 6
#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ 4
#define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT 2
#define SUN8I_AIF_CLK_CTRL(n) (0x040 * (1 + (n)))
#define SUN8I_AIF_CLK_CTRL_MSTR_MOD 15
#define SUN8I_AIF_CLK_CTRL_CLK_INV 13
#define SUN8I_AIF_CLK_CTRL_BCLK_DIV 9
#define SUN8I_AIF_CLK_CTRL_LRCK_DIV 6
#define SUN8I_AIF_CLK_CTRL_WORD_SIZ 4
#define SUN8I_AIF_CLK_CTRL_DATA_FMT 2
#define SUN8I_AIF1_ADCDAT_CTRL 0x044
#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA 15
#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA 14
@ -88,11 +88,11 @@
#define SUN8I_SYSCLK_CTL_AIF2CLK_SRC_MASK GENMASK(5, 4)
#define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK GENMASK(15, 12)
#define SUN8I_SYS_SR_CTRL_AIF2_FS_MASK GENMASK(11, 8)
#define SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV_MASK GENMASK(14, 13)
#define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK GENMASK(12, 9)
#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK GENMASK(8, 6)
#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK GENMASK(5, 4)
#define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK GENMASK(3, 2)
#define SUN8I_AIF_CLK_CTRL_CLK_INV_MASK GENMASK(14, 13)
#define SUN8I_AIF_CLK_CTRL_BCLK_DIV_MASK GENMASK(12, 9)
#define SUN8I_AIF_CLK_CTRL_LRCK_DIV_MASK GENMASK(8, 6)
#define SUN8I_AIF_CLK_CTRL_WORD_SIZ_MASK GENMASK(5, 4)
#define SUN8I_AIF_CLK_CTRL_DATA_FMT_MASK GENMASK(3, 2)
#define SUN8I_CODEC_PASSTHROUGH_SAMPLE_RATE 48000
@ -241,9 +241,10 @@ static int sun8i_codec_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
default:
return -EINVAL;
}
regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
BIT(SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD),
value << SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD);
regmap_update_bits(scodec->regmap, SUN8I_AIF_CLK_CTRL(dai->id),
BIT(SUN8I_AIF_CLK_CTRL_MSTR_MOD),
value << SUN8I_AIF_CLK_CTRL_MSTR_MOD);
/* DAI format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
@ -267,9 +268,10 @@ static int sun8i_codec_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
default:
return -EINVAL;
}
regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK,
format << SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT);
regmap_update_bits(scodec->regmap, SUN8I_AIF_CLK_CTRL(dai->id),
SUN8I_AIF_CLK_CTRL_DATA_FMT_MASK,
format << SUN8I_AIF_CLK_CTRL_DATA_FMT);
/* clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
@ -310,9 +312,9 @@ static int sun8i_codec_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
invert ^= scodec->quirks->lrck_inversion;
}
regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV_MASK,
invert << SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV);
regmap_update_bits(scodec->regmap, SUN8I_AIF_CLK_CTRL(dai->id),
SUN8I_AIF_CLK_CTRL_CLK_INV_MASK,
invert << SUN8I_AIF_CLK_CTRL_CLK_INV);
return 0;
}
@ -459,27 +461,27 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream,
return -EINVAL;
}
regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK,
word_size << SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ);
regmap_update_bits(scodec->regmap, SUN8I_AIF_CLK_CTRL(dai->id),
SUN8I_AIF_CLK_CTRL_WORD_SIZ_MASK,
word_size << SUN8I_AIF_CLK_CTRL_WORD_SIZ);
/* LRCK divider (BCLK/LRCK ratio) */
lrck_div_order = sun8i_codec_get_lrck_div_order(slots, slot_width);
if (lrck_div_order < 0)
return lrck_div_order;
regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK,
(lrck_div_order - 4) << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV);
regmap_update_bits(scodec->regmap, SUN8I_AIF_CLK_CTRL(dai->id),
SUN8I_AIF_CLK_CTRL_LRCK_DIV_MASK,
(lrck_div_order - 4) << SUN8I_AIF_CLK_CTRL_LRCK_DIV);
/* BCLK divider (SYSCLK/BCLK ratio) */
bclk_div = sun8i_codec_get_bclk_div(sysclk_rate, lrck_div_order, sample_rate);
if (bclk_div < 0)
return bclk_div;
regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK,
bclk_div << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV);
regmap_update_bits(scodec->regmap, SUN8I_AIF_CLK_CTRL(dai->id),
SUN8I_AIF_CLK_CTRL_BCLK_DIV_MASK,
bclk_div << SUN8I_AIF_CLK_CTRL_BCLK_DIV);
/*
* SYSCLK rate