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powerpc/book3e-64: Use hardcoded mttmr opcode 

This preserves the ability to build using older binutils (reportedly <=
2.22).

Fixes: 6becef7ea0 ("powerpc/mpc85xx: Add CPU hotplug support for E6500")
Signed-off-by: Scott Wood <oss@buserror.net>
Cc: chenhui.zhao@freescale.com
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Scott Wood 2016-03-15 01:47:38 -05:00 committed by Michael Ellerman
parent a1b5344620
commit 7a25d91214
1 changed files with 5 additions and 4 deletions
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9
arch/powerpc/kernel/head_64.S
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@ -41,6 +41,7 @@
#include <asm/ptrace.h> #include <asm/ptrace.h>
#include <asm/hw_irq.h> #include <asm/hw_irq.h>
#include <asm/cputhreads.h> #include <asm/cputhreads.h>
#include <asm/ppc-opcode.h>
/* The physical memory is laid out such that the secondary processor /* The physical memory is laid out such that the secondary processor
* spin code sits at 0x0000...0x00ff. On server, the vectors follow * spin code sits at 0x0000...0x00ff. On server, the vectors follow
@ -207,12 +208,12 @@ _GLOBAL(book3e_start_thread)
/* If the thread id is invalid, just exit. */ /* If the thread id is invalid, just exit. */
b 13f b 13f
10: 10:
mttmr TMRN_IMSR0, r5 MTTMR(TMRN_IMSR0, 5)
mttmr TMRN_INIA0, r4 MTTMR(TMRN_INIA0, 4)
b 12f b 12f
11: 11:
mttmr TMRN_IMSR1, r5 MTTMR(TMRN_IMSR1, 5)
mttmr TMRN_INIA1, r4 MTTMR(TMRN_INIA1, 4)
12: 12:
isync isync
li r6, 1 li r6, 1