[media] s5p-fimc: Fix output DMA handling in S5PV310 IP revisions

FIMC IP in S5Pv310 series has extended DMA status registers
and some bit fields are marked as reserved comparing to S5PC100/110.
Use correct registers for getting DMA write pointer in each SoC variant
supported by the driver.

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Sylwester Nawrocki 2010-11-25 10:49:21 -03:00 committed by Mauro Carvalho Chehab
parent a8365fc205
commit 798174ab62
4 changed files with 19 additions and 3 deletions

View File

@ -522,6 +522,7 @@ static int fimc_cap_streamon(struct file *file, void *priv,
INIT_LIST_HEAD(&fimc->vid_cap.active_buf_q); INIT_LIST_HEAD(&fimc->vid_cap.active_buf_q);
fimc->vid_cap.active_buf_cnt = 0; fimc->vid_cap.active_buf_cnt = 0;
fimc->vid_cap.frame_count = 0; fimc->vid_cap.frame_count = 0;
fimc->vid_cap.buf_index = fimc_hw_get_frame_index(fimc);
set_bit(ST_CAPT_PEND, &fimc->state); set_bit(ST_CAPT_PEND, &fimc->state);
ret = videobuf_streamon(&fimc->vid_cap.vbq); ret = videobuf_streamon(&fimc->vid_cap.vbq);

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@ -1746,6 +1746,7 @@ static struct samsung_fimc_variant fimc0_variant_s5pv310 = {
.pix_hoff = 1, .pix_hoff = 1,
.has_inp_rot = 1, .has_inp_rot = 1,
.has_out_rot = 1, .has_out_rot = 1,
.has_cistatus2 = 1,
.min_inp_pixsize = 16, .min_inp_pixsize = 16,
.min_out_pixsize = 16, .min_out_pixsize = 16,
.hor_offs_align = 1, .hor_offs_align = 1,
@ -1755,6 +1756,7 @@ static struct samsung_fimc_variant fimc0_variant_s5pv310 = {
static struct samsung_fimc_variant fimc2_variant_s5pv310 = { static struct samsung_fimc_variant fimc2_variant_s5pv310 = {
.pix_hoff = 1, .pix_hoff = 1,
.has_cistatus2 = 1,
.min_inp_pixsize = 16, .min_inp_pixsize = 16,
.min_out_pixsize = 16, .min_out_pixsize = 16,
.hor_offs_align = 1, .hor_offs_align = 1,

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@ -371,6 +371,7 @@ struct fimc_pix_limit {
* @pix_hoff: indicate whether horizontal offset is in pixels or in bytes * @pix_hoff: indicate whether horizontal offset is in pixels or in bytes
* @has_inp_rot: set if has input rotator * @has_inp_rot: set if has input rotator
* @has_out_rot: set if has output rotator * @has_out_rot: set if has output rotator
* @has_cistatus2: 1 if CISTATUS2 register is present in this IP revision
* @pix_limit: pixel size constraints for the scaler * @pix_limit: pixel size constraints for the scaler
* @min_inp_pixsize: minimum input pixel size * @min_inp_pixsize: minimum input pixel size
* @min_out_pixsize: minimum output pixel size * @min_out_pixsize: minimum output pixel size
@ -381,6 +382,7 @@ struct samsung_fimc_variant {
unsigned int pix_hoff:1; unsigned int pix_hoff:1;
unsigned int has_inp_rot:1; unsigned int has_inp_rot:1;
unsigned int has_out_rot:1; unsigned int has_out_rot:1;
unsigned int has_cistatus2:1;
struct fimc_pix_limit *pix_limit; struct fimc_pix_limit *pix_limit;
u16 min_inp_pixsize; u16 min_inp_pixsize;
u16 min_out_pixsize; u16 min_out_pixsize;
@ -556,11 +558,19 @@ static inline struct fimc_frame *ctx_get_frame(struct fimc_ctx *ctx,
return frame; return frame;
} }
/* Return an index to the buffer actually being written. */
static inline u32 fimc_hw_get_frame_index(struct fimc_dev *dev) static inline u32 fimc_hw_get_frame_index(struct fimc_dev *dev)
{ {
u32 reg = readl(dev->regs + S5P_CISTATUS); u32 reg;
return (reg & S5P_CISTATUS_FRAMECNT_MASK) >>
S5P_CISTATUS_FRAMECNT_SHIFT; if (dev->variant->has_cistatus2) {
reg = readl(dev->regs + S5P_CISTATUS2) & 0x3F;
return reg > 0 ? --reg : reg;
} else {
reg = readl(dev->regs + S5P_CISTATUS);
return (reg & S5P_CISTATUS_FRAMECNT_MASK) >>
S5P_CISTATUS_FRAMECNT_SHIFT;
}
} }
/* -----------------------------------------------------*/ /* -----------------------------------------------------*/

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@ -165,6 +165,9 @@
#define S5P_CISTATUS_VVALID_A (1 << 15) #define S5P_CISTATUS_VVALID_A (1 << 15)
#define S5P_CISTATUS_VVALID_B (1 << 14) #define S5P_CISTATUS_VVALID_B (1 << 14)
/* Indexes to the last and the currently processed buffer. */
#define S5P_CISTATUS2 0x68
/* Image capture control */ /* Image capture control */
#define S5P_CIIMGCPT 0xc0 #define S5P_CIIMGCPT 0xc0
#define S5P_CIIMGCPT_IMGCPTEN (1 << 31) #define S5P_CIIMGCPT_IMGCPTEN (1 << 31)