[media] s5p-fimc: Fix output DMA handling in S5PV310 IP revisions
FIMC IP in S5Pv310 series has extended DMA status registers and some bit fields are marked as reserved comparing to S5PC100/110. Use correct registers for getting DMA write pointer in each SoC variant supported by the driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
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@ -522,6 +522,7 @@ static int fimc_cap_streamon(struct file *file, void *priv,
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INIT_LIST_HEAD(&fimc->vid_cap.active_buf_q);
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INIT_LIST_HEAD(&fimc->vid_cap.active_buf_q);
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fimc->vid_cap.active_buf_cnt = 0;
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fimc->vid_cap.active_buf_cnt = 0;
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fimc->vid_cap.frame_count = 0;
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fimc->vid_cap.frame_count = 0;
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fimc->vid_cap.buf_index = fimc_hw_get_frame_index(fimc);
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set_bit(ST_CAPT_PEND, &fimc->state);
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set_bit(ST_CAPT_PEND, &fimc->state);
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ret = videobuf_streamon(&fimc->vid_cap.vbq);
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ret = videobuf_streamon(&fimc->vid_cap.vbq);
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@ -1746,6 +1746,7 @@ static struct samsung_fimc_variant fimc0_variant_s5pv310 = {
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.pix_hoff = 1,
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.pix_hoff = 1,
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.has_inp_rot = 1,
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.has_inp_rot = 1,
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.has_out_rot = 1,
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.has_out_rot = 1,
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.has_cistatus2 = 1,
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.min_inp_pixsize = 16,
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.min_inp_pixsize = 16,
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.min_out_pixsize = 16,
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.min_out_pixsize = 16,
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.hor_offs_align = 1,
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.hor_offs_align = 1,
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@ -1755,6 +1756,7 @@ static struct samsung_fimc_variant fimc0_variant_s5pv310 = {
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static struct samsung_fimc_variant fimc2_variant_s5pv310 = {
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static struct samsung_fimc_variant fimc2_variant_s5pv310 = {
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.pix_hoff = 1,
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.pix_hoff = 1,
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.has_cistatus2 = 1,
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.min_inp_pixsize = 16,
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.min_inp_pixsize = 16,
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.min_out_pixsize = 16,
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.min_out_pixsize = 16,
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.hor_offs_align = 1,
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.hor_offs_align = 1,
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@ -371,6 +371,7 @@ struct fimc_pix_limit {
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* @pix_hoff: indicate whether horizontal offset is in pixels or in bytes
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* @pix_hoff: indicate whether horizontal offset is in pixels or in bytes
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* @has_inp_rot: set if has input rotator
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* @has_inp_rot: set if has input rotator
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* @has_out_rot: set if has output rotator
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* @has_out_rot: set if has output rotator
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* @has_cistatus2: 1 if CISTATUS2 register is present in this IP revision
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* @pix_limit: pixel size constraints for the scaler
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* @pix_limit: pixel size constraints for the scaler
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* @min_inp_pixsize: minimum input pixel size
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* @min_inp_pixsize: minimum input pixel size
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* @min_out_pixsize: minimum output pixel size
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* @min_out_pixsize: minimum output pixel size
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@ -381,6 +382,7 @@ struct samsung_fimc_variant {
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unsigned int pix_hoff:1;
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unsigned int pix_hoff:1;
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unsigned int has_inp_rot:1;
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unsigned int has_inp_rot:1;
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unsigned int has_out_rot:1;
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unsigned int has_out_rot:1;
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unsigned int has_cistatus2:1;
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struct fimc_pix_limit *pix_limit;
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struct fimc_pix_limit *pix_limit;
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u16 min_inp_pixsize;
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u16 min_inp_pixsize;
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u16 min_out_pixsize;
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u16 min_out_pixsize;
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@ -556,11 +558,19 @@ static inline struct fimc_frame *ctx_get_frame(struct fimc_ctx *ctx,
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return frame;
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return frame;
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}
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}
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/* Return an index to the buffer actually being written. */
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static inline u32 fimc_hw_get_frame_index(struct fimc_dev *dev)
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static inline u32 fimc_hw_get_frame_index(struct fimc_dev *dev)
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{
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{
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u32 reg = readl(dev->regs + S5P_CISTATUS);
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u32 reg;
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return (reg & S5P_CISTATUS_FRAMECNT_MASK) >>
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S5P_CISTATUS_FRAMECNT_SHIFT;
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if (dev->variant->has_cistatus2) {
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reg = readl(dev->regs + S5P_CISTATUS2) & 0x3F;
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return reg > 0 ? --reg : reg;
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} else {
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reg = readl(dev->regs + S5P_CISTATUS);
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return (reg & S5P_CISTATUS_FRAMECNT_MASK) >>
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S5P_CISTATUS_FRAMECNT_SHIFT;
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}
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}
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}
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/* -----------------------------------------------------*/
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/* -----------------------------------------------------*/
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@ -165,6 +165,9 @@
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#define S5P_CISTATUS_VVALID_A (1 << 15)
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#define S5P_CISTATUS_VVALID_A (1 << 15)
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#define S5P_CISTATUS_VVALID_B (1 << 14)
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#define S5P_CISTATUS_VVALID_B (1 << 14)
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/* Indexes to the last and the currently processed buffer. */
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#define S5P_CISTATUS2 0x68
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/* Image capture control */
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/* Image capture control */
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#define S5P_CIIMGCPT 0xc0
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#define S5P_CIIMGCPT 0xc0
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#define S5P_CIIMGCPT_IMGCPTEN (1 << 31)
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#define S5P_CIIMGCPT_IMGCPTEN (1 << 31)
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