arm64: Add TCR_EPD{0,1} definitions
We are soon going to play with TCR_EL1.EPD{0,1}, so let's add the relevant definitions. Reviewed-by: James Morse <james.morse@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
parent
bfae1b98ef
commit
793d5d9213
|
@ -224,6 +224,8 @@
|
|||
#define TCR_TxSZ_WIDTH 6
|
||||
#define TCR_T0SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T0SZ_OFFSET)
|
||||
|
||||
#define TCR_EPD0_SHIFT 7
|
||||
#define TCR_EPD0_MASK (UL(1) << TCR_EPD0_SHIFT)
|
||||
#define TCR_IRGN0_SHIFT 8
|
||||
#define TCR_IRGN0_MASK (UL(3) << TCR_IRGN0_SHIFT)
|
||||
#define TCR_IRGN0_NC (UL(0) << TCR_IRGN0_SHIFT)
|
||||
|
@ -231,6 +233,8 @@
|
|||
#define TCR_IRGN0_WT (UL(2) << TCR_IRGN0_SHIFT)
|
||||
#define TCR_IRGN0_WBnWA (UL(3) << TCR_IRGN0_SHIFT)
|
||||
|
||||
#define TCR_EPD1_SHIFT 23
|
||||
#define TCR_EPD1_MASK (UL(1) << TCR_EPD1_SHIFT)
|
||||
#define TCR_IRGN1_SHIFT 24
|
||||
#define TCR_IRGN1_MASK (UL(3) << TCR_IRGN1_SHIFT)
|
||||
#define TCR_IRGN1_NC (UL(0) << TCR_IRGN1_SHIFT)
|
||||
|
|
Loading…
Reference in New Issue