usb: dwc3: ep0: add dwc3_ep0_prepare_one_trb()
For now this is just a cleanup patch, no functional changes. We will be using the new function to fix a bug introduced long ago by commit0416e494ce
("usb: dwc3: ep0: correct cache sync issue in case of ep0_bounced") and further worsened by commitc0bd5456a4
("usb: dwc3: ep0: handle non maxpacket aligned transfers > 512") Cc: <stable@vger.kernel.org> Reported-by: Janusz Dziedzic <januszx.dziedzic@linux.intel.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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@ -39,18 +39,13 @@ static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
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static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
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struct dwc3_ep *dep, struct dwc3_request *req);
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static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
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u32 len, u32 type, bool chain)
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static void dwc3_ep0_prepare_one_trb(struct dwc3 *dwc, u8 epnum,
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dma_addr_t buf_dma, u32 len, u32 type, bool chain)
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{
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struct dwc3_gadget_ep_cmd_params params;
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struct dwc3_trb *trb;
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struct dwc3_ep *dep;
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int ret;
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dep = dwc->eps[epnum];
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if (dep->flags & DWC3_EP_BUSY)
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return 0;
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trb = &dwc->ep0_trb[dep->trb_enqueue];
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@ -71,15 +66,26 @@ static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
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trb->ctrl |= (DWC3_TRB_CTRL_IOC
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| DWC3_TRB_CTRL_LST);
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if (chain)
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trace_dwc3_prepare_trb(dep, trb);
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}
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static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
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u32 len, u32 type, bool chain)
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{
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struct dwc3_gadget_ep_cmd_params params;
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struct dwc3_ep *dep;
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int ret;
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dep = dwc->eps[epnum];
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if (dep->flags & DWC3_EP_BUSY)
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return 0;
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dwc3_ep0_prepare_one_trb(dwc, epnum, buf_dma, len, type, chain);
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memset(¶ms, 0, sizeof(params));
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params.param0 = upper_32_bits(dwc->ep0_trb_addr);
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params.param1 = lower_32_bits(dwc->ep0_trb_addr);
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trace_dwc3_prepare_trb(dep, trb);
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ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, ¶ms);
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if (ret < 0)
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return ret;
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