[MIPS] Pb1000 code style cleanup
Fix several errors and warnings given by checkpatch.pl: - use of C99 // comments; - brace not on the same line with condition in the 'switch' statement; - printk() without KERN_* facility level; - unnecessary braces for single-statement block; - using simple_strtol() where strict_strtol() could be used. In addition to these changes, also do the following: - properly indent the 'switch' statement; - remove needless parentheses; - insert spaces between operator and its operands; - replace numeric literals/expressions with the matching macros; - remove useless #if dirctive from board_setup(); - remove unneeded numeric literal type casts; - remove space after the type cast's closing parenthesis; - replace spaces after the macro name with tabs in the #define directives, and sometimes insert spaces there; - remove excess new lines; - fix typos/errors, capitalize acronyms, etc. in the comments; - make the multi-line comment style consistent with the kernel style elsewhere by adding empty first/last line; - combine some comments; - update MontaVista copyright; - remove Pete Popov's old email address... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Sergei Shtylyov
Ralf Baechle
parent
abd14cc00d
commit
7916c3548e
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@ -1,8 +1,8 @@
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#
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# Copyright 2000 MontaVista Software Inc.
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# Author: MontaVista Software, Inc.
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# ppopov@mvista.com or source@mvista.com
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# Copyright 2000, 2008 MontaVista Software Inc.
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# Author: MontaVista Software, Inc. <source@mvista.com>
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#
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# Makefile for the Alchemy Semiconductor Pb1000 board.
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#
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# Makefile for the Alchemy Semiconductor PB1000 board.
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lib-y := init.o board_setup.o irqmap.o
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@ -1,7 +1,6 @@
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/*
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* Copyright 2000 MontaVista Software Inc.
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* Author: MontaVista Software, Inc.
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* ppopov@mvista.com or source@mvista.com
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* Copyright 2000, 2008 MontaVista Software Inc.
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* Author: MontaVista Software, Inc. <source@mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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@ -40,106 +39,108 @@ void __init board_setup(void)
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u32 sys_freqctrl, sys_clksrc;
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u32 prid = read_c0_prid();
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// set AUX clock to 12MHz * 8 = 96 MHz
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/* Set AUX clock to 12 MHz * 8 = 96 MHz */
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au_writel(8, SYS_AUXPLL);
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au_writel(0, SYS_PINSTATERD);
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udelay(100);
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#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
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/* zero and disable FREQ2 */
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/* Zero and disable FREQ2 */
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sys_freqctrl = au_readl(SYS_FREQCTRL0);
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sys_freqctrl &= ~0xFFF00000;
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au_writel(sys_freqctrl, SYS_FREQCTRL0);
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/* zero and disable USBH/USBD clocks */
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/* Zero and disable USBH/USBD clocks */
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sys_clksrc = au_readl(SYS_CLKSRC);
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sys_clksrc &= ~0x00007FE0;
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sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
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SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
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au_writel(sys_clksrc, SYS_CLKSRC);
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sys_freqctrl = au_readl(SYS_FREQCTRL0);
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sys_freqctrl &= ~0xFFF00000;
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sys_clksrc = au_readl(SYS_CLKSRC);
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sys_clksrc &= ~0x00007FE0;
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sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
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SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
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switch (prid & 0x000000FF)
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{
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switch (prid & 0x000000FF) {
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case 0x00: /* DA */
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case 0x01: /* HA */
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case 0x02: /* HB */
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/* CPU core freq to 48MHz to slow it way down... */
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au_writel(4, SYS_CPUPLL);
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/* CPU core freq to 48 MHz to slow it way down... */
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au_writel(4, SYS_CPUPLL);
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/*
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* Setup 48MHz FREQ2 from CPUPLL for USB Host
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*/
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/* FRDIV2=3 -> div by 8 of 384MHz -> 48MHz */
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sys_freqctrl |= ((3<<22) | (1<<21) | (0<<20));
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au_writel(sys_freqctrl, SYS_FREQCTRL0);
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/*
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* Setup 48 MHz FREQ2 from CPUPLL for USB Host
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* FRDIV2 = 3 -> div by 8 of 384 MHz -> 48 MHz
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*/
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sys_freqctrl |= (3 << SYS_FC_FRDIV2_BIT) | SYS_FC_FE2;
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au_writel(sys_freqctrl, SYS_FREQCTRL0);
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/* CPU core freq to 384MHz */
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au_writel(0x20, SYS_CPUPLL);
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/* CPU core freq to 384 MHz */
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au_writel(0x20, SYS_CPUPLL);
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printk("Au1000: 48MHz OHCI workaround enabled\n");
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printk(KERN_INFO "Au1000: 48 MHz OHCI workaround enabled\n");
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break;
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default: /* HC and newer */
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// FREQ2 = aux/2 = 48 MHz
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sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20));
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au_writel(sys_freqctrl, SYS_FREQCTRL0);
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default: /* HC and newer */
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/* FREQ2 = aux / 2 = 48 MHz */
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sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) |
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SYS_FC_FE2 | SYS_FC_FS2;
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au_writel(sys_freqctrl, SYS_FREQCTRL0);
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break;
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}
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/*
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* Route 48MHz FREQ2 into USB Host and/or Device
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* Route 48 MHz FREQ2 into USB Host and/or Device
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*/
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#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
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sys_clksrc |= ((4<<12) | (0<<11) | (0<<10));
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#endif
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sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MUH_BIT;
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au_writel(sys_clksrc, SYS_CLKSRC);
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// configure pins GPIO[14:9] as GPIO
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pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8080);
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/* Configure pins GPIO[14:9] as GPIO */
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pin_func = au_readl(SYS_PINFUNC) & ~(SYS_PF_UR3 | SYS_PF_USB);
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// 2nd USB port is USB host
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pin_func |= 0x8000;
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/* 2nd USB port is USB host */
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pin_func |= SYS_PF_USB;
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au_writel(pin_func, SYS_PINFUNC);
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au_writel(0x2800, SYS_TRIOUTCLR);
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au_writel(0x0030, SYS_OUTPUTCLR);
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#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
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// make gpio 15 an input (for interrupt line)
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pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x100);
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// we don't need I2S, so make it available for GPIO[31:29]
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pin_func |= (1<<5);
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/* Make GPIO 15 an input (for interrupt line) */
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pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_IRF;
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/* We don't need I2S, so make it available for GPIO[31:29] */
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pin_func |= SYS_PF_I2S;
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au_writel(pin_func, SYS_PINFUNC);
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au_writel(0x8000, SYS_TRIOUTCLR);
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static_cfg0 = au_readl(MEM_STCFG0) & (u32)(~0xc00);
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static_cfg0 = au_readl(MEM_STCFG0) & ~0xc00;
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au_writel(static_cfg0, MEM_STCFG0);
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// configure RCE2* for LCD
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/* configure RCE2* for LCD */
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au_writel(0x00000004, MEM_STCFG2);
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// MEM_STTIME2
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/* MEM_STTIME2 */
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au_writel(0x09000000, MEM_STTIME2);
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// Set 32-bit base address decoding for RCE2*
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/* Set 32-bit base address decoding for RCE2* */
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au_writel(0x10003ff0, MEM_STADDR2);
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// PCI CPLD setup
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// expand CE0 to cover PCI
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/*
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* PCI CPLD setup
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* Expand CE0 to cover PCI
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*/
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au_writel(0x11803e40, MEM_STADDR1);
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// burst visibility on
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/* Burst visibility on */
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au_writel(au_readl(MEM_STCFG0) | 0x1000, MEM_STCFG0);
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au_writel(0x83, MEM_STCFG1); // ewait enabled, flash timing
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au_writel(0x33030a10, MEM_STTIME1); // slower timing for FPGA
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au_writel(0x83, MEM_STCFG1); /* ewait enabled, flash timing */
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au_writel(0x33030a10, MEM_STTIME1); /* slower timing for FPGA */
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/* setup the static bus controller */
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/* Setup the static bus controller */
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au_writel(0x00000002, MEM_STCFG3); /* type = PCMCIA */
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au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */
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au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */
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@ -151,17 +152,20 @@ void __init board_setup(void)
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au_sync_delay(1);
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#endif
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/* Enable Au1000 BCLK switching - note: sed1356 must not use
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* its BCLK (Au1000 LCLK) for any timings */
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switch (prid & 0x000000FF)
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{
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/*
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* Enable Au1000 BCLK switching - note: sed1356 must not use
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* its BCLK (Au1000 LCLK) for any timings
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*/
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switch (prid & 0x000000FF) {
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case 0x00: /* DA */
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case 0x01: /* HA */
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case 0x02: /* HB */
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break;
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default: /* HC and newer */
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/* Enable sys bus clock divider when IDLE state or no bus
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activity. */
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/*
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* Enable sys bus clock divider when IDLE state or no bus
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* activity.
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*/
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au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
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break;
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}
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@ -1,10 +1,9 @@
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/*
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* BRIEF MODULE DESCRIPTION
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* PB1000 board setup
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* Pb1000 board setup
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*
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* Copyright 2001 MontaVista Software Inc.
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* Author: MontaVista Software, Inc.
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* ppopov@mvista.com or source@mvista.com
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* Copyright 2001, 2008 MontaVista Software Inc.
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* Author: MontaVista Software, Inc. <source@mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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@ -44,16 +43,15 @@ void __init prom_init(void)
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unsigned char *memsize_str;
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unsigned long memsize;
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prom_argc = (int) fw_arg0;
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prom_argv = (char **) fw_arg1;
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prom_envp = (char **) fw_arg2;
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prom_argc = (int)fw_arg0;
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prom_argv = (char **)fw_arg1;
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prom_envp = (char **)fw_arg2;
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prom_init_cmdline();
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memsize_str = prom_getenv("memsize");
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if (!memsize_str) {
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if (!memsize_str)
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memsize = 0x04000000;
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} else {
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memsize = simple_strtol(memsize_str, NULL, 0);
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}
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else
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memsize = strict_strtol(memsize_str, 0, NULL);
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add_memory_region(0, memsize, BOOT_MEM_RAM);
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}
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@ -1,9 +1,8 @@
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/*
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* Alchemy Semi PB1000 Referrence Board
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* Alchemy Semi Pb1000 Referrence Board
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*
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* Copyright 2001 MontaVista Software Inc.
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* Author: MontaVista Software, Inc.
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* ppopov@mvista.com or source@mvista.com
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* Copyright 2001, 2008 MontaVista Software Inc.
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* Author: MontaVista Software, Inc. <source@mvista.com>
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*
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* ########################################################################
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*
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@ -28,145 +27,61 @@
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#define __ASM_PB1000_H
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/* PCMCIA PB1000 specific defines */
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#define PCMCIA_MAX_SOCK 1
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#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
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#define PCMCIA_MAX_SOCK 1
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#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
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#define PB1000_PCR 0xBE000000
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# define PCR_SLOT_0_VPP0 (1<<0)
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# define PCR_SLOT_0_VPP1 (1<<1)
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# define PCR_SLOT_0_VCC0 (1<<2)
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# define PCR_SLOT_0_VCC1 (1<<3)
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# define PCR_SLOT_0_RST (1<<4)
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#define PB1000_PCR 0xBE000000
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# define PCR_SLOT_0_VPP0 (1 << 0)
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# define PCR_SLOT_0_VPP1 (1 << 1)
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# define PCR_SLOT_0_VCC0 (1 << 2)
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# define PCR_SLOT_0_VCC1 (1 << 3)
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# define PCR_SLOT_0_RST (1 << 4)
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# define PCR_SLOT_1_VPP0 (1 << 8)
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# define PCR_SLOT_1_VPP1 (1 << 9)
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# define PCR_SLOT_1_VCC0 (1 << 10)
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# define PCR_SLOT_1_VCC1 (1 << 11)
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# define PCR_SLOT_1_RST (1 << 12)
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# define PCR_SLOT_1_VPP0 (1<<8)
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# define PCR_SLOT_1_VPP1 (1<<9)
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# define PCR_SLOT_1_VCC0 (1<<10)
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# define PCR_SLOT_1_VCC1 (1<<11)
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# define PCR_SLOT_1_RST (1<<12)
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#define PB1000_MDR 0xBE000004
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# define MDR_PI (1 << 5) /* PCMCIA int latch */
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# define MDR_EPI (1 << 14) /* enable PCMCIA int */
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# define MDR_CPI (1 << 15) /* clear PCMCIA int */
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#define PB1000_MDR 0xBE000004
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# define MDR_PI (1<<5) /* pcmcia int latch */
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# define MDR_EPI (1<<14) /* enable pcmcia int */
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# define MDR_CPI (1<<15) /* clear pcmcia int */
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#define PB1000_ACR1 0xBE000008
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# define ACR1_SLOT_0_CD1 (1 << 0) /* card detect 1 */
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# define ACR1_SLOT_0_CD2 (1 << 1) /* card detect 2 */
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# define ACR1_SLOT_0_READY (1 << 2) /* ready */
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# define ACR1_SLOT_0_STATUS (1 << 3) /* status change */
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# define ACR1_SLOT_0_VS1 (1 << 4) /* voltage sense 1 */
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# define ACR1_SLOT_0_VS2 (1 << 5) /* voltage sense 2 */
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# define ACR1_SLOT_0_INPACK (1 << 6) /* inpack pin status */
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# define ACR1_SLOT_1_CD1 (1 << 8) /* card detect 1 */
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# define ACR1_SLOT_1_CD2 (1 << 9) /* card detect 2 */
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# define ACR1_SLOT_1_READY (1 << 10) /* ready */
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# define ACR1_SLOT_1_STATUS (1 << 11) /* status change */
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# define ACR1_SLOT_1_VS1 (1 << 12) /* voltage sense 1 */
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# define ACR1_SLOT_1_VS2 (1 << 13) /* voltage sense 2 */
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# define ACR1_SLOT_1_INPACK (1 << 14) /* inpack pin status */
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#define PB1000_ACR1 0xBE000008
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# define ACR1_SLOT_0_CD1 (1<<0) /* card detect 1 */
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# define ACR1_SLOT_0_CD2 (1<<1) /* card detect 2 */
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# define ACR1_SLOT_0_READY (1<<2) /* ready */
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# define ACR1_SLOT_0_STATUS (1<<3) /* status change */
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# define ACR1_SLOT_0_VS1 (1<<4) /* voltage sense 1 */
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# define ACR1_SLOT_0_VS2 (1<<5) /* voltage sense 2 */
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# define ACR1_SLOT_0_INPACK (1<<6) /* inpack pin status */
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# define ACR1_SLOT_1_CD1 (1<<8) /* card detect 1 */
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# define ACR1_SLOT_1_CD2 (1<<9) /* card detect 2 */
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# define ACR1_SLOT_1_READY (1<<10) /* ready */
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# define ACR1_SLOT_1_STATUS (1<<11) /* status change */
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# define ACR1_SLOT_1_VS1 (1<<12) /* voltage sense 1 */
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# define ACR1_SLOT_1_VS2 (1<<13) /* voltage sense 2 */
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# define ACR1_SLOT_1_INPACK (1<<14) /* inpack pin status */
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#define CPLD_AUX0 0xBE00000C
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#define CPLD_AUX1 0xBE000010
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#define CPLD_AUX2 0xBE000014
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#define CPLD_AUX0 0xBE00000C
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#define CPLD_AUX1 0xBE000010
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#define CPLD_AUX2 0xBE000014
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/* Voltage levels */
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/* VPPEN1 - VPPEN0 */
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#define VPP_GND ((0<<1) | (0<<0))
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#define VPP_5V ((1<<1) | (0<<0))
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#define VPP_3V ((0<<1) | (1<<0))
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#define VPP_12V ((0<<1) | (1<<0))
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#define VPP_HIZ ((1<<1) | (1<<0))
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#define VPP_GND ((0 << 1) | (0 << 0))
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#define VPP_5V ((1 << 1) | (0 << 0))
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#define VPP_3V ((0 << 1) | (1 << 0))
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#define VPP_12V ((0 << 1) | (1 << 0))
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#define VPP_HIZ ((1 << 1) | (1 << 0))
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/* VCCEN1 - VCCEN0 */
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#define VCC_3V ((0<<1) | (1<<0))
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#define VCC_5V ((1<<1) | (0<<0))
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#define VCC_HIZ ((0<<1) | (0<<0))
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#define VCC_3V ((0 << 1) | (1 << 0))
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#define VCC_5V ((1 << 1) | (0 << 0))
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#define VCC_HIZ ((0 << 1) | (0 << 0))
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/* VPP/VCC */
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#define SET_VCC_VPP(VCC, VPP, SLOT)\
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((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
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/* PCI PB1000 specific defines */
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/* The reason these defines are here instead of au1000.h is because
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* the Au1000 does not have a PCI bus controller so the PCI implementation
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* on the some of the older Pb1000 boards was very board specific.
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*/
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#define PCI_CONFIG_BASE 0xBA020000 /* the only external slot */
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#define SDRAM_DEVID 0xBA010000
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#define SDRAM_CMD 0xBA010004
|
||||
#define SDRAM_CLASS 0xBA010008
|
||||
#define SDRAM_MISC 0xBA01000C
|
||||
#define SDRAM_MBAR 0xBA010010
|
||||
|
||||
#define PCI_IO_DATA_PORT 0xBA800000
|
||||
|
||||
#define PCI_IO_ADDR 0xBE00001C
|
||||
#define PCI_INT_ACK 0xBBC00000
|
||||
#define PCI_IO_READ 0xBBC00020
|
||||
#define PCI_IO_WRITE 0xBBC00030
|
||||
|
||||
#define PCI_BRIDGE_CONFIG 0xBE000018
|
||||
|
||||
#define PCI_IO_START 0x10000000
|
||||
#define PCI_IO_END 0x1000ffff
|
||||
#define PCI_MEM_START 0x18000000
|
||||
#define PCI_MEM_END 0x18ffffff
|
||||
|
||||
#define PCI_FIRST_DEVFN 0
|
||||
#define PCI_LAST_DEVFN 1
|
||||
|
||||
static inline u8 au_pci_io_readb(u32 addr)
|
||||
{
|
||||
writel(addr, PCI_IO_ADDR);
|
||||
writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<12), PCI_BRIDGE_CONFIG);
|
||||
return (readl(PCI_IO_DATA_PORT) & 0xff);
|
||||
}
|
||||
|
||||
static inline u16 au_pci_io_readw(u32 addr)
|
||||
{
|
||||
writel(addr, PCI_IO_ADDR);
|
||||
writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<13), PCI_BRIDGE_CONFIG);
|
||||
return (readl(PCI_IO_DATA_PORT) & 0xffff);
|
||||
}
|
||||
|
||||
static inline u32 au_pci_io_readl(u32 addr)
|
||||
{
|
||||
writel(addr, PCI_IO_ADDR);
|
||||
writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff), PCI_BRIDGE_CONFIG);
|
||||
return readl(PCI_IO_DATA_PORT);
|
||||
}
|
||||
|
||||
static inline void au_pci_io_writeb(u8 val, u32 addr)
|
||||
{
|
||||
writel(addr, PCI_IO_ADDR);
|
||||
writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<12), PCI_BRIDGE_CONFIG);
|
||||
writel(val, PCI_IO_DATA_PORT);
|
||||
}
|
||||
|
||||
static inline void au_pci_io_writew(u16 val, u32 addr)
|
||||
{
|
||||
writel(addr, PCI_IO_ADDR);
|
||||
writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<13), PCI_BRIDGE_CONFIG);
|
||||
writel(val, PCI_IO_DATA_PORT);
|
||||
}
|
||||
|
||||
static inline void au_pci_io_writel(u32 val, u32 addr)
|
||||
{
|
||||
writel(addr, PCI_IO_ADDR);
|
||||
writel(readl(PCI_BRIDGE_CONFIG) & 0xffffcfff, PCI_BRIDGE_CONFIG);
|
||||
writel(val, PCI_IO_DATA_PORT);
|
||||
}
|
||||
|
||||
static inline void set_sdram_extbyte(void)
|
||||
{
|
||||
writel(readl(PCI_BRIDGE_CONFIG) & 0xffffff00, PCI_BRIDGE_CONFIG);
|
||||
}
|
||||
|
||||
static inline void set_slot_extbyte(void)
|
||||
{
|
||||
writel((readl(PCI_BRIDGE_CONFIG) & 0xffffbf00) | 0x18, PCI_BRIDGE_CONFIG);
|
||||
}
|
||||
#define SET_VCC_VPP(VCC, VPP, SLOT) \
|
||||
((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
|
||||
#endif /* __ASM_PB1000_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue