diff --git a/Documentation/sh/index.rst b/Documentation/sh/index.rst index 967acad9ff5e..b5933fd399f3 100644 --- a/Documentation/sh/index.rst +++ b/Documentation/sh/index.rst @@ -8,6 +8,7 @@ SuperH Interfaces Guide :maxdepth: 1 new-machine + register-banks Memory Management ================= diff --git a/Documentation/sh/register-banks.txt b/Documentation/sh/register-banks.rst similarity index 88% rename from Documentation/sh/register-banks.txt rename to Documentation/sh/register-banks.rst index a6719f2f6594..2bef5c8fcbbc 100644 --- a/Documentation/sh/register-banks.txt +++ b/Documentation/sh/register-banks.rst @@ -1,5 +1,8 @@ - Notes on register bank usage in the kernel - ========================================== +.. SPDX-License-Identifier: GPL-2.0 + +========================================== +Notes on register bank usage in the kernel +========================================== Introduction ------------ @@ -23,11 +26,15 @@ Presently the kernel uses several of these registers. - r0_bank, r1_bank (referenced as k0 and k1, used for scratch registers when doing exception handling). + - r2_bank (used to track the EXPEVT/INTEVT code) + - Used by do_IRQ() and friends for doing irq mapping based off of the interrupt exception vector jump table offset + - r6_bank (global interrupt mask) + - The SR.IMASK interrupt handler makes use of this to set the interrupt priority level (used by local_irq_enable()) - - r7_bank (current) + - r7_bank (current) diff --git a/arch/sh/Kconfig.cpu b/arch/sh/Kconfig.cpu index 97ca35f2cd37..fff419f3d757 100644 --- a/arch/sh/Kconfig.cpu +++ b/arch/sh/Kconfig.cpu @@ -85,7 +85,7 @@ config CPU_HAS_SR_RB that are lacking this bit must have another method in place for accomplishing what is taken care of by the banked registers. - See for further + See for further information on SR.RB and register banking in the kernel in general. config CPU_HAS_PTEAEX