diff --git a/Documentation/devicetree/bindings/arm/xilinx.yaml b/Documentation/devicetree/bindings/arm/xilinx.yaml index 97e77b4e077c..f52c7e8ce654 100644 --- a/Documentation/devicetree/bindings/arm/xilinx.yaml +++ b/Documentation/devicetree/bindings/arm/xilinx.yaml @@ -22,6 +22,9 @@ properties: - adapteva,parallella - digilent,zynq-zybo - digilent,zynq-zybo-z7 + - ebang,ebaz4205 + - myir,zynq-zturn-v5 + - myir,zynq-zturn - xlnx,zynq-cc108 - xlnx,zynq-zc702 - xlnx,zynq-zc706 diff --git a/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt b/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt deleted file mode 100644 index 16b734ad3102..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt +++ /dev/null @@ -1,25 +0,0 @@ -Xilinx Zynq QSPI controller Device Tree Bindings -------------------------------------------------------------------- - -Required properties: -- compatible : Should be "xlnx,zynq-qspi-1.0". -- reg : Physical base address and size of QSPI registers map. -- interrupts : Property with a value describing the interrupt - number. -- clock-names : List of input clock names - "ref_clk", "pclk" - (See clock bindings for details). -- clocks : Clock phandles (see clock bindings for details). - -Optional properties: -- num-cs : Number of chip selects used. - -Example: - qspi: spi@e000d000 { - compatible = "xlnx,zynq-qspi-1.0"; - reg = <0xe000d000 0x1000>; - interrupt-parent = <&intc>; - interrupts = <0 19 4>; - clock-names = "ref_clk", "pclk"; - clocks = <&clkc 10>, <&clkc 43>; - num-cs = <1>; - }; diff --git a/Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml b/Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml new file mode 100644 index 000000000000..1f1c40a9f320 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/xlnx,zynq-qspi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Zynq QSPI controller + +description: + The Xilinx Zynq QSPI controller is used to access multi-bit serial flash + memory devices. + +allOf: + - $ref: "spi-controller.yaml#" + +maintainers: + - Michal Simek + +# Everything else is described in the common file +properties: + compatible: + const: xlnx,zynq-qspi-1.0 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: reference clock + - description: peripheral clock + + clock-names: + items: + - const: ref_clk + - const: pclk + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + spi@e000d000 { + compatible = "xlnx,zynq-qspi-1.0"; + reg = <0xe000d000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <0 19 4>; + clock-names = "ref_clk", "pclk"; + clocks = <&clkc 10>, <&clkc 43>; + num-cs = <1>; + }; diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index ee6a6843e412..3b2958202258 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -313,6 +313,8 @@ patternProperties: description: Dyna-Image "^ea,.*": description: Embedded Artists AB + "^ebang,.*": + description: Zhejiang Ebang Communication Co., Ltd "^ebs-systart,.*": description: EBS-SYSTART GmbH "^ebv,.*": diff --git a/MAINTAINERS b/MAINTAINERS index 4dd5cc054372..7c5aa4ffb0ff 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2768,6 +2768,7 @@ W: http://wiki.xilinx.com T: git https://github.com/Xilinx/linux-xlnx.git F: Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml F: Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml +F: Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml F: arch/arm/mach-zynq/ F: drivers/block/xsysace.c F: drivers/clocksource/timer-cadence-ttc.c diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index bbb09ced0744..f127ddcf8df7 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1322,6 +1322,7 @@ dtb-$(CONFIG_ARCH_VT8500) += \ wm8850-w70v2.dtb dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-cc108.dtb \ + zynq-ebaz4205.dtb \ zynq-microzed.dtb \ zynq-parallella.dtb \ zynq-zc702.dtb \ diff --git a/arch/arm/boot/dts/zynq-ebaz4205.dts b/arch/arm/boot/dts/zynq-ebaz4205.dts new file mode 100644 index 000000000000..b0b836aedd76 --- /dev/null +++ b/arch/arm/boot/dts/zynq-ebaz4205.dts @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Michael Walle + */ +/dts-v1/; +/include/ "zynq-7000.dtsi" + +/ { + model = "Ebang EBAZ4205"; + compatible = "ebang,ebaz4205", "xlnx,zynq-7000"; + + aliases { + ethernet0 = &gem0; + serial0 = &uart1; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x10000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&clkc { + ps-clk-frequency = <33333333>; + fclk-enable = <8>; +}; + +&gem0 { + status = "okay"; + phy-mode = "mii"; + phy-handle = <&phy>; + + /* PHY clock */ + assigned-clocks = <&clkc 18>; + assigned-clock-rates = <25000000>; + + phy: ethernet-phy@0 { + reg = <0>; + }; +}; + +&gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio0_default>; +}; + +&pinctrl0 { + pinctrl_gpio0_default: gpio0-default { + mux { + groups = "gpio0_20_grp", "gpio0_32_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_20_grp", "gpio0_32_grp"; + io-standard = <3>; + slew-rate = <0>; + }; + + conf-pull-up { + pins = "MIO20", "MIO32"; + bias-disable; + }; + }; + + pinctrl_sdhci0_default: sdhci0-default { + mux { + groups = "sdio0_2_grp"; + function = "sdio0"; + }; + + conf { + groups = "sdio0_2_grp"; + io-standard = <3>; + slew-rate = <0>; + bias-disable; + }; + + mux-cd { + groups = "gpio0_34_grp"; + function = "sdio0_cd"; + }; + + conf-cd { + groups = "gpio0_34_grp"; + io-standard = <3>; + slew-rate = <0>; + bias-high-impedance; + bias-pull-up; + }; + }; + + pinctrl_uart1_default: uart1-default { + mux { + groups = "uart1_4_grp"; + function = "uart1"; + }; + + conf { + groups = "uart1_4_grp"; + io-standard = <3>; + slew-rate = <0>; + }; + + conf-rx { + pins = "MIO25"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO24"; + bias-disable; + }; + }; +}; + +&sdhci0 { + status = "okay"; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci0_default>; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; +};