mt76: mt7915: rework debugfs queue info
Complete PSE/PLE queue statistics, including per-sta AC queue information. Co-developed-by: Sujuan Chen <sujuan.chen@mediatek.com> Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Felix Fietkau <nbd@nbd.name>
This commit is contained in:
Ryder Lee
Felix Fietkau
parent
0ab947c3dc
commit
776ec4e77a
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@ -7,6 +7,13 @@
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/** global debugfs **/
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struct hw_queue_map {
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const char *name;
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u8 index;
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u8 pid;
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u8 qid;
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};
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static int
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mt7915_implicit_txbf_set(void *data, u64 val)
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{
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@ -233,30 +240,131 @@ mt7915_tx_stats_show(struct seq_file *file, void *data)
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DEFINE_SHOW_ATTRIBUTE(mt7915_tx_stats);
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static int
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mt7915_queues_acq(struct seq_file *s, void *data)
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static void
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mt7915_hw_queue_read(struct seq_file *s, u32 base, u32 size,
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const struct hw_queue_map *map)
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{
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struct mt7915_dev *dev = dev_get_drvdata(s->private);
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int i;
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u32 i, val;
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for (i = 0; i < 16; i++) {
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int j, acs = i / 4, index = i % 4;
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u32 ctrl, val, qlen = 0;
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val = mt76_rr(dev, base + MT_FL_Q_EMPTY);
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for (i = 0; i < size; i++) {
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u32 ctrl, head, tail, queued;
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val = mt76_rr(dev, MT_PLE_AC_QEMPTY(acs, index));
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ctrl = BIT(31) | BIT(15) | (acs << 8);
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for (j = 0; j < 32; j++) {
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if (val & BIT(j))
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if (val & BIT(map[i].index))
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continue;
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mt76_wr(dev, MT_PLE_FL_Q0_CTRL,
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ctrl | (j + (index << 5)));
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qlen += mt76_get_field(dev, MT_PLE_FL_Q3_CTRL,
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ctrl = BIT(31) | (map[i].pid << 10) | (map[i].qid << 24);
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mt76_wr(dev, base + MT_FL_Q0_CTRL, ctrl);
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head = mt76_get_field(dev, base + MT_FL_Q2_CTRL,
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GENMASK(11, 0));
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tail = mt76_get_field(dev, base + MT_FL_Q2_CTRL,
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GENMASK(27, 16));
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queued = mt76_get_field(dev, base + MT_FL_Q3_CTRL,
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GENMASK(11, 0));
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seq_printf(s, "\t%s: ", map[i].name);
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seq_printf(s, "queued:0x%03x head:0x%03x tail:0x%03x\n",
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queued, head, tail);
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}
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seq_printf(s, "AC%d%d: queued=%d\n", acs, index, qlen);
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}
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static void
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mt7915_sta_hw_queue_read(void *data, struct ieee80211_sta *sta)
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{
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struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv;
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struct mt7915_dev *dev = msta->vif->phy->dev;
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struct seq_file *s = data;
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u8 ac;
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for (ac = 0; ac < 4; ac++) {
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u32 qlen, ctrl, val;
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u32 idx = msta->wcid.idx >> 5;
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u8 offs = msta->wcid.idx & GENMASK(4, 0);
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ctrl = BIT(31) | BIT(11) | (ac << 24);
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val = mt76_rr(dev, MT_PLE_AC_QEMPTY(ac, idx));
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if (val & BIT(offs))
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continue;
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mt76_wr(dev, MT_PLE_BASE + MT_FL_Q0_CTRL, ctrl | msta->wcid.idx);
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qlen = mt76_get_field(dev, MT_PLE_BASE + MT_FL_Q3_CTRL,
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GENMASK(11, 0));
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seq_printf(s, "\tSTA %pM wcid %d: AC%d%d queued:%d\n",
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sta->addr, msta->wcid.idx, msta->vif->wmm_idx,
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ac, qlen);
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}
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}
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static int
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mt7915_hw_queues_read(struct seq_file *s, void *data)
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{
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struct mt7915_dev *dev = dev_get_drvdata(s->private);
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struct mt7915_phy *phy = mt7915_ext_phy(dev);
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static const struct hw_queue_map ple_queue_map[] = {
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{"CPU_Q0", 0, 1, MT_CTX0},
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{"CPU_Q1", 1, 1, MT_CTX0 + 1},
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{"CPU_Q2", 2, 1, MT_CTX0 + 2},
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{"CPU_Q3", 3, 1, MT_CTX0 + 3},
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{"ALTX_Q0", 8, 2, MT_LMAC_ALTX0},
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{"BMC_Q0", 9, 2, MT_LMAC_BMC0},
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{"BCN_Q0", 10, 2, MT_LMAC_BCN0},
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{"PSMP_Q0", 11, 2, MT_LMAC_PSMP0},
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{"ALTX_Q1", 12, 2, MT_LMAC_ALTX0 + 4},
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{"BMC_Q1", 13, 2, MT_LMAC_BMC0 + 4},
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{"BCN_Q1", 14, 2, MT_LMAC_BCN0 + 4},
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{"PSMP_Q1", 15, 2, MT_LMAC_PSMP0 + 4},
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};
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static const struct hw_queue_map pse_queue_map[] = {
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{"CPU Q0", 0, 1, MT_CTX0},
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{"CPU Q1", 1, 1, MT_CTX0 + 1},
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{"CPU Q2", 2, 1, MT_CTX0 + 2},
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{"CPU Q3", 3, 1, MT_CTX0 + 3},
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{"HIF_Q0", 8, 0, MT_HIF0},
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{"HIF_Q1", 9, 0, MT_HIF0 + 1},
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{"HIF_Q2", 10, 0, MT_HIF0 + 2},
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{"HIF_Q3", 11, 0, MT_HIF0 + 3},
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{"HIF_Q4", 12, 0, MT_HIF0 + 4},
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{"HIF_Q5", 13, 0, MT_HIF0 + 5},
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{"LMAC_Q", 16, 2, 0},
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{"MDP_TXQ", 17, 2, 1},
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{"MDP_RXQ", 18, 2, 2},
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{"SEC_TXQ", 19, 2, 3},
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{"SEC_RXQ", 20, 2, 4},
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};
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u32 val, head, tail;
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/* ple queue */
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val = mt76_rr(dev, MT_PLE_FREEPG_CNT);
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head = mt76_get_field(dev, MT_PLE_FREEPG_HEAD_TAIL, GENMASK(11, 0));
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tail = mt76_get_field(dev, MT_PLE_FREEPG_HEAD_TAIL, GENMASK(27, 16));
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seq_puts(s, "PLE page info:\n");
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seq_printf(s, "\tTotal free page: 0x%08x head: 0x%03x tail: 0x%03x\n",
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val, head, tail);
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val = mt76_rr(dev, MT_PLE_PG_HIF_GROUP);
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head = mt76_get_field(dev, MT_PLE_HIF_PG_INFO, GENMASK(11, 0));
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tail = mt76_get_field(dev, MT_PLE_HIF_PG_INFO, GENMASK(27, 16));
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seq_printf(s, "\tHIF free page: 0x%03x res: 0x%03x used: 0x%03x\n",
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val, head, tail);
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seq_puts(s, "PLE non-empty queue info:\n");
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mt7915_hw_queue_read(s, MT_PLE_BASE, ARRAY_SIZE(ple_queue_map),
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&ple_queue_map[0]);
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/* iterate per-sta ple queue */
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ieee80211_iterate_stations_atomic(dev->mphy.hw,
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mt7915_sta_hw_queue_read, s);
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if (phy)
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ieee80211_iterate_stations_atomic(phy->mt76->hw,
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mt7915_sta_hw_queue_read, s);
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/* pse queue */
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seq_puts(s, "PSE non-empty queue info:\n");
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mt7915_hw_queue_read(s, MT_PSE_BASE, ARRAY_SIZE(pse_queue_map),
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&pse_queue_map[0]);
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return 0;
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}
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@ -345,8 +453,8 @@ int mt7915_init_debugfs(struct mt7915_dev *dev)
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debugfs_create_devm_seqfile(dev->mt76.dev, "queues", dir,
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mt7915_queues_read);
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debugfs_create_devm_seqfile(dev->mt76.dev, "acq", dir,
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mt7915_queues_acq);
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debugfs_create_devm_seqfile(dev->mt76.dev, "hw-queues", dir,
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mt7915_hw_queues_read);
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debugfs_create_file("tx_stats", 0400, dir, dev, &mt7915_tx_stats_fops);
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debugfs_create_file("fw_debug", 0600, dir, dev, &fops_fw_debug);
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debugfs_create_file("implicit_txbf", 0600, dir, dev,
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@ -379,9 +487,23 @@ static int mt7915_sta_fixed_rate_set(void *data, u64 rate)
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DEFINE_DEBUGFS_ATTRIBUTE(fops_fixed_rate, NULL,
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mt7915_sta_fixed_rate_set, "%llx\n");
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static int
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mt7915_queues_show(struct seq_file *s, void *data)
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{
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struct ieee80211_sta *sta = s->private;
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mt7915_sta_hw_queue_read(s, sta);
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return 0;
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}
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DEFINE_SHOW_ATTRIBUTE(mt7915_queues);
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void mt7915_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
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struct ieee80211_sta *sta, struct dentry *dir)
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{
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debugfs_create_file("fixed_rate", 0600, dir, sta, &fops_fixed_rate);
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debugfs_create_file("hw-queues", 0400, dir, sta, &mt7915_queues_fops);
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}
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#endif
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@ -205,13 +205,17 @@ enum {
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};
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enum {
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MT_LMAC_AC00,
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MT_CTX0,
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MT_HIF0 = 0x0,
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MT_LMAC_AC00 = 0x0,
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MT_LMAC_AC01,
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MT_LMAC_AC02,
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MT_LMAC_AC03,
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MT_LMAC_ALTX0 = 0x10,
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MT_LMAC_BMC0,
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MT_LMAC_BCN0,
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MT_LMAC_PSMP0,
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};
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enum {
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@ -22,15 +22,22 @@
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#define MT_PLE_BASE 0x8000
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#define MT_PLE(ofs) (MT_PLE_BASE + (ofs))
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#define MT_PLE_FL_Q0_CTRL MT_PLE(0x1b0)
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#define MT_PLE_FL_Q1_CTRL MT_PLE(0x1b4)
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#define MT_PLE_FL_Q2_CTRL MT_PLE(0x1b8)
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#define MT_PLE_FL_Q3_CTRL MT_PLE(0x1bc)
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#define MT_FL_Q_EMPTY 0x0b0
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#define MT_FL_Q0_CTRL 0x1b0
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#define MT_FL_Q2_CTRL 0x1b8
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#define MT_FL_Q3_CTRL 0x1bc
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#define MT_PLE_AC_QEMPTY(ac, n) MT_PLE(0x300 + 0x10 * (ac) + \
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#define MT_PLE_FREEPG_CNT MT_PLE(0x100)
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#define MT_PLE_FREEPG_HEAD_TAIL MT_PLE(0x104)
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#define MT_PLE_PG_HIF_GROUP MT_PLE(0x110)
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#define MT_PLE_HIF_PG_INFO MT_PLE(0x114)
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#define MT_PLE_AC_QEMPTY(ac, n) MT_PLE(0x500 + 0x40 * (ac) + \
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((n) << 2))
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#define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2))
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#define MT_PSE_BASE 0xc000
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#define MT_PSE(ofs) (MT_PSE_BASE + (ofs))
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#define MT_MDP_BASE 0xf000
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#define MT_MDP(ofs) (MT_MDP_BASE + (ofs))
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