Merge branch 'net-hns3-updates-for-next'
Huazhong Tan says:
====================
net: hns3: updates for -next
This patchset adds dump tm info of nodes, priority and qset in debugfs.
Three debugfs files tm_nodes, tm_priority and tm_qset are created in
new tm directory, and use cat command to dump their info, for examples:
$ cat tm_nodes
BASE_ID MAX_NUM
PG 0 8
PRI 0 8
QSET 0 8
QUEUE 0 1024
$ cat tm_priority
ID MODE DWRR C_IR_B C_IR_U C_IR_S C_BS_B C_BS_S C_FLAG C_RATE(Mbps) P_IR_B P_IR_U P_IR_S P_BS_B P_BS_S P_FLAG P_RATE(Mbps)
0000 dwrr 100 0 0 0 5 20 0 0 150 7 0 5 20 0 0
0001 sp 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0002 sp 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0003 sp 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0004 sp 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0005 sp 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0006 sp 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0007 sp 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
$ cat tm_qset
ID MAP_PRI LINK_VLD MODE DWRR
0000 0 1 dwrr 100
0001 0 0 sp 0
0002 0 0 sp 0
0003 0 0 sp 0
0004 0 0 sp 0
0005 0 0 sp 0
0006 0 0 sp 0
change log:
V2: add readonly files for dump all nodes, priority and qset info
suggested by Jakub Kicinski.
previous version:
V1: https://patchwork.kernel.org/project/netdevbpf/patch/1610694569-43099-1-git-send-email-tanhuazhong@huawei.com/
====================
Link: https://lore.kernel.org/r/1611834696-56207-1-git-send-email-tanhuazhong@huawei.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski
commit
77609b1db2
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@ -465,6 +465,8 @@ struct hnae3_ae_dev {
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* Delete clsflower rule
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* cls_flower_active
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* Check if any cls flower rule exist
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* dbg_read_cmd
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* Execute debugfs read command.
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*/
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struct hnae3_ae_ops {
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int (*init_ae_dev)(struct hnae3_ae_dev *ae_dev);
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@ -620,6 +622,8 @@ struct hnae3_ae_ops {
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int (*add_arfs_entry)(struct hnae3_handle *handle, u16 queue_id,
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u16 flow_id, struct flow_keys *fkeys);
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int (*dbg_run_cmd)(struct hnae3_handle *handle, const char *cmd_buf);
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int (*dbg_read_cmd)(struct hnae3_handle *handle, const char *cmd_buf,
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char *buf, int len);
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pci_ers_result_t (*handle_hw_ras_error)(struct hnae3_ae_dev *ae_dev);
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bool (*get_hw_reset_stat)(struct hnae3_handle *handle);
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bool (*ae_dev_resetting)(struct hnae3_handle *handle);
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@ -777,6 +781,10 @@ struct hnae3_handle {
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#define hnae3_get_bit(origin, shift) \
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hnae3_get_field((origin), (0x1 << (shift)), (shift))
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#define HNAE3_DBG_TM_NODES "tm_nodes"
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#define HNAE3_DBG_TM_PRI "tm_priority"
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#define HNAE3_DBG_TM_QSET "tm_qset"
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int hnae3_register_ae_dev(struct hnae3_ae_dev *ae_dev);
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void hnae3_unregister_ae_dev(struct hnae3_ae_dev *ae_dev);
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@ -7,7 +7,7 @@
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#include "hnae3.h"
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#include "hns3_enet.h"
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#define HNS3_DBG_READ_LEN 256
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#define HNS3_DBG_READ_LEN 65536
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#define HNS3_DBG_WRITE_LEN 1024
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static struct dentry *hns3_dbgfs_root;
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@ -484,6 +484,42 @@ static ssize_t hns3_dbg_cmd_write(struct file *filp, const char __user *buffer,
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return count;
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}
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static ssize_t hns3_dbg_read(struct file *filp, char __user *buffer,
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size_t count, loff_t *ppos)
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{
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struct hnae3_handle *handle = filp->private_data;
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const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
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struct hns3_nic_priv *priv = handle->priv;
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char *cmd_buf, *read_buf;
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ssize_t size = 0;
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int ret = 0;
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if (!filp->f_path.dentry->d_iname)
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return -EINVAL;
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read_buf = kzalloc(HNS3_DBG_READ_LEN, GFP_KERNEL);
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if (!read_buf)
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return -ENOMEM;
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cmd_buf = filp->f_path.dentry->d_iname;
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if (ops->dbg_read_cmd)
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ret = ops->dbg_read_cmd(handle, cmd_buf, read_buf,
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HNS3_DBG_READ_LEN);
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if (ret) {
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dev_info(priv->dev, "unknown command\n");
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goto out;
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}
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size = simple_read_from_buffer(buffer, count, ppos, read_buf,
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strlen(read_buf));
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out:
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kfree(read_buf);
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return size;
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}
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static const struct file_operations hns3_dbg_cmd_fops = {
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.owner = THIS_MODULE,
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.open = simple_open,
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@ -491,14 +527,31 @@ static const struct file_operations hns3_dbg_cmd_fops = {
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.write = hns3_dbg_cmd_write,
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};
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static const struct file_operations hns3_dbg_fops = {
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.owner = THIS_MODULE,
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.open = simple_open,
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.read = hns3_dbg_read,
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};
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void hns3_dbg_init(struct hnae3_handle *handle)
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{
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struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
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const char *name = pci_name(handle->pdev);
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struct dentry *entry_dir;
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handle->hnae3_dbgfs = debugfs_create_dir(name, hns3_dbgfs_root);
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debugfs_create_file("cmd", 0600, handle->hnae3_dbgfs, handle,
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&hns3_dbg_cmd_fops);
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entry_dir = debugfs_create_dir("tm", handle->hnae3_dbgfs);
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if (ae_dev->dev_version > HNAE3_DEVICE_VERSION_V2)
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debugfs_create_file(HNAE3_DBG_TM_NODES, 0600, entry_dir, handle,
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&hns3_dbg_fops);
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debugfs_create_file(HNAE3_DBG_TM_PRI, 0600, entry_dir, handle,
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&hns3_dbg_fops);
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debugfs_create_file(HNAE3_DBG_TM_QSET, 0600, entry_dir, handle,
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&hns3_dbg_fops);
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}
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void hns3_dbg_uninit(struct hnae3_handle *handle)
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|
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@ -160,6 +160,7 @@ enum hclge_opcode_type {
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HCLGE_OPC_TM_PRI_SCH_MODE_CFG = 0x0813,
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HCLGE_OPC_TM_QS_SCH_MODE_CFG = 0x0814,
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HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815,
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HCLGE_OPC_TM_NODES = 0x0816,
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HCLGE_OPC_ETS_TC_WEIGHT = 0x0843,
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HCLGE_OPC_QSET_DFX_STS = 0x0844,
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HCLGE_OPC_PRI_DFX_STS = 0x0845,
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@ -800,6 +800,140 @@ err_tm_map_cmd_send:
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cmd, ret);
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}
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static int hclge_dbg_dump_tm_nodes(struct hclge_dev *hdev, char *buf, int len)
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{
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struct hclge_tm_nodes_cmd *nodes;
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struct hclge_desc desc;
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int pos = 0;
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int ret;
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hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_NODES, true);
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ret = hclge_cmd_send(&hdev->hw, &desc, 1);
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if (ret) {
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dev_err(&hdev->pdev->dev,
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"failed to dump tm nodes, ret = %d\n", ret);
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return ret;
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}
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nodes = (struct hclge_tm_nodes_cmd *)desc.data;
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pos += scnprintf(buf + pos, len - pos, " BASE_ID MAX_NUM\n");
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pos += scnprintf(buf + pos, len - pos, "PG %4u %4u\n",
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nodes->pg_base_id, nodes->pg_num);
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pos += scnprintf(buf + pos, len - pos, "PRI %4u %4u\n",
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nodes->pri_base_id, nodes->pri_num);
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pos += scnprintf(buf + pos, len - pos, "QSET %4u %4u\n",
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le16_to_cpu(nodes->qset_base_id),
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le16_to_cpu(nodes->qset_num));
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pos += scnprintf(buf + pos, len - pos, "QUEUE %4u %4u\n",
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le16_to_cpu(nodes->queue_base_id),
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le16_to_cpu(nodes->queue_num));
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return 0;
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}
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static int hclge_dbg_dump_tm_pri(struct hclge_dev *hdev, char *buf, int len)
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{
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struct hclge_pri_shaper_para c_shaper_para;
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struct hclge_pri_shaper_para p_shaper_para;
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u8 pri_num, sch_mode, weight;
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char *sch_mode_str;
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int pos = 0;
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int ret;
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u8 i;
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ret = hclge_tm_get_pri_num(hdev, &pri_num);
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if (ret)
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return ret;
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pos += scnprintf(buf + pos, len - pos,
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"ID MODE DWRR C_IR_B C_IR_U C_IR_S C_BS_B ");
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pos += scnprintf(buf + pos, len - pos,
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"C_BS_S C_FLAG C_RATE(Mbps) P_IR_B P_IR_U ");
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pos += scnprintf(buf + pos, len - pos,
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"P_IR_S P_BS_B P_BS_S P_FLAG P_RATE(Mbps)\n");
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for (i = 0; i < pri_num; i++) {
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ret = hclge_tm_get_pri_sch_mode(hdev, i, &sch_mode);
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if (ret)
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return ret;
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ret = hclge_tm_get_pri_weight(hdev, i, &weight);
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if (ret)
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return ret;
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ret = hclge_tm_get_pri_shaper(hdev, i,
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HCLGE_OPC_TM_PRI_C_SHAPPING,
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&c_shaper_para);
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if (ret)
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return ret;
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ret = hclge_tm_get_pri_shaper(hdev, i,
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HCLGE_OPC_TM_PRI_P_SHAPPING,
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&p_shaper_para);
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if (ret)
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return ret;
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sch_mode_str = sch_mode & HCLGE_TM_TX_SCHD_DWRR_MSK ? "dwrr" :
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"sp";
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pos += scnprintf(buf + pos, len - pos,
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"%04u %4s %3u %3u %3u %3u ",
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i, sch_mode_str, weight, c_shaper_para.ir_b,
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c_shaper_para.ir_u, c_shaper_para.ir_s);
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pos += scnprintf(buf + pos, len - pos,
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"%3u %3u %1u %6u ",
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c_shaper_para.bs_b, c_shaper_para.bs_s,
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c_shaper_para.flag, c_shaper_para.rate);
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pos += scnprintf(buf + pos, len - pos,
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"%3u %3u %3u %3u %3u ",
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p_shaper_para.ir_b, p_shaper_para.ir_u,
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p_shaper_para.ir_s, p_shaper_para.bs_b,
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p_shaper_para.bs_s);
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pos += scnprintf(buf + pos, len - pos, "%1u %6u\n",
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p_shaper_para.flag, p_shaper_para.rate);
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}
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return 0;
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}
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static int hclge_dbg_dump_tm_qset(struct hclge_dev *hdev, char *buf, int len)
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{
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u8 priority, link_vld, sch_mode, weight;
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char *sch_mode_str;
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int ret, pos;
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u16 qset_num;
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u16 i;
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ret = hclge_tm_get_qset_num(hdev, &qset_num);
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if (ret)
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return ret;
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pos = scnprintf(buf, len, "ID MAP_PRI LINK_VLD MODE DWRR\n");
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for (i = 0; i < qset_num; i++) {
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ret = hclge_tm_get_qset_map_pri(hdev, i, &priority, &link_vld);
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if (ret)
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return ret;
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ret = hclge_tm_get_qset_sch_mode(hdev, i, &sch_mode);
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if (ret)
|
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return ret;
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ret = hclge_tm_get_qset_weight(hdev, i, &weight);
|
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if (ret)
|
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return ret;
|
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|
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sch_mode_str = sch_mode & HCLGE_TM_TX_SCHD_DWRR_MSK ? "dwrr" :
|
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"sp";
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pos += scnprintf(buf + pos, len - pos,
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"%04u %4u %1u %4s %3u\n",
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i, priority, link_vld, sch_mode_str, weight);
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}
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|
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return 0;
|
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}
|
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|
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static void hclge_dbg_dump_qos_pause_cfg(struct hclge_dev *hdev)
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{
|
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struct hclge_cfg_pause_param_cmd *pause_param;
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|
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@ -1591,3 +1725,22 @@ int hclge_dbg_run_cmd(struct hnae3_handle *handle, const char *cmd_buf)
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|
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return 0;
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}
|
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|
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int hclge_dbg_read_cmd(struct hnae3_handle *handle, const char *cmd_buf,
|
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char *buf, int len)
|
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{
|
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struct hclge_vport *vport = hclge_get_vport(handle);
|
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struct hclge_dev *hdev = vport->back;
|
||||
|
||||
if (strncmp(cmd_buf, HNAE3_DBG_TM_NODES,
|
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strlen(HNAE3_DBG_TM_NODES)) == 0)
|
||||
return hclge_dbg_dump_tm_nodes(hdev, buf, len);
|
||||
else if (strncmp(cmd_buf, HNAE3_DBG_TM_PRI,
|
||||
strlen(HNAE3_DBG_TM_PRI)) == 0)
|
||||
return hclge_dbg_dump_tm_pri(hdev, buf, len);
|
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else if (strncmp(cmd_buf, HNAE3_DBG_TM_QSET,
|
||||
strlen(HNAE3_DBG_TM_QSET)) == 0)
|
||||
return hclge_dbg_dump_tm_qset(hdev, buf, len);
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -11850,6 +11850,7 @@ static const struct hnae3_ae_ops hclge_ops = {
|
|||
.enable_fd = hclge_enable_fd,
|
||||
.add_arfs_entry = hclge_add_fd_entry_by_arfs,
|
||||
.dbg_run_cmd = hclge_dbg_run_cmd,
|
||||
.dbg_read_cmd = hclge_dbg_read_cmd,
|
||||
.handle_hw_ras_error = hclge_handle_hw_ras_error,
|
||||
.get_hw_reset_stat = hclge_get_hw_reset_stat,
|
||||
.ae_dev_resetting = hclge_ae_dev_resetting,
|
||||
|
|
|
|||
|
|
@ -1006,6 +1006,8 @@ int hclge_vport_start(struct hclge_vport *vport);
|
|||
void hclge_vport_stop(struct hclge_vport *vport);
|
||||
int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu);
|
||||
int hclge_dbg_run_cmd(struct hnae3_handle *handle, const char *cmd_buf);
|
||||
int hclge_dbg_read_cmd(struct hnae3_handle *handle, const char *cmd_buf,
|
||||
char *buf, int len);
|
||||
u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id);
|
||||
int hclge_notify_client(struct hclge_dev *hdev,
|
||||
enum hnae3_reset_notify_type type);
|
||||
|
|
|
|||
|
|
@ -1616,3 +1616,189 @@ int hclge_tm_vport_map_update(struct hclge_dev *hdev)
|
|||
|
||||
return hclge_tm_bp_setup(hdev);
|
||||
}
|
||||
|
||||
int hclge_tm_get_qset_num(struct hclge_dev *hdev, u16 *qset_num)
|
||||
{
|
||||
struct hclge_tm_nodes_cmd *nodes;
|
||||
struct hclge_desc desc;
|
||||
int ret;
|
||||
|
||||
if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2) {
|
||||
/* Each PF has 8 qsets and each VF has 1 qset */
|
||||
*qset_num = HCLGE_TM_PF_MAX_QSET_NUM + pci_num_vf(hdev->pdev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_NODES, true);
|
||||
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
|
||||
if (ret) {
|
||||
dev_err(&hdev->pdev->dev,
|
||||
"failed to get qset num, ret = %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
nodes = (struct hclge_tm_nodes_cmd *)desc.data;
|
||||
*qset_num = le16_to_cpu(nodes->qset_num);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int hclge_tm_get_pri_num(struct hclge_dev *hdev, u8 *pri_num)
|
||||
{
|
||||
struct hclge_tm_nodes_cmd *nodes;
|
||||
struct hclge_desc desc;
|
||||
int ret;
|
||||
|
||||
if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2) {
|
||||
*pri_num = HCLGE_TM_PF_MAX_PRI_NUM;
|
||||
return 0;
|
||||
}
|
||||
|
||||
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_NODES, true);
|
||||
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
|
||||
if (ret) {
|
||||
dev_err(&hdev->pdev->dev,
|
||||
"failed to get pri num, ret = %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
nodes = (struct hclge_tm_nodes_cmd *)desc.data;
|
||||
*pri_num = nodes->pri_num;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int hclge_tm_get_qset_map_pri(struct hclge_dev *hdev, u16 qset_id, u8 *priority,
|
||||
u8 *link_vld)
|
||||
{
|
||||
struct hclge_qs_to_pri_link_cmd *map;
|
||||
struct hclge_desc desc;
|
||||
int ret;
|
||||
|
||||
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_TO_PRI_LINK, true);
|
||||
map = (struct hclge_qs_to_pri_link_cmd *)desc.data;
|
||||
map->qs_id = cpu_to_le16(qset_id);
|
||||
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
|
||||
if (ret) {
|
||||
dev_err(&hdev->pdev->dev,
|
||||
"failed to get qset map priority, ret = %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
*priority = map->priority;
|
||||
*link_vld = map->link_vld;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int hclge_tm_get_qset_sch_mode(struct hclge_dev *hdev, u16 qset_id, u8 *mode)
|
||||
{
|
||||
struct hclge_qs_sch_mode_cfg_cmd *qs_sch_mode;
|
||||
struct hclge_desc desc;
|
||||
int ret;
|
||||
|
||||
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_SCH_MODE_CFG, true);
|
||||
qs_sch_mode = (struct hclge_qs_sch_mode_cfg_cmd *)desc.data;
|
||||
qs_sch_mode->qs_id = cpu_to_le16(qset_id);
|
||||
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
|
||||
if (ret) {
|
||||
dev_err(&hdev->pdev->dev,
|
||||
"failed to get qset sch mode, ret = %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
*mode = qs_sch_mode->sch_mode;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int hclge_tm_get_qset_weight(struct hclge_dev *hdev, u16 qset_id, u8 *weight)
|
||||
{
|
||||
struct hclge_qs_weight_cmd *qs_weight;
|
||||
struct hclge_desc desc;
|
||||
int ret;
|
||||
|
||||
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_WEIGHT, true);
|
||||
qs_weight = (struct hclge_qs_weight_cmd *)desc.data;
|
||||
qs_weight->qs_id = cpu_to_le16(qset_id);
|
||||
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
|
||||
if (ret) {
|
||||
dev_err(&hdev->pdev->dev,
|
||||
"failed to get qset weight, ret = %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
*weight = qs_weight->dwrr;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int hclge_tm_get_pri_sch_mode(struct hclge_dev *hdev, u8 pri_id, u8 *mode)
|
||||
{
|
||||
struct hclge_pri_sch_mode_cfg_cmd *pri_sch_mode;
|
||||
struct hclge_desc desc;
|
||||
int ret;
|
||||
|
||||
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PRI_SCH_MODE_CFG, true);
|
||||
pri_sch_mode = (struct hclge_pri_sch_mode_cfg_cmd *)desc.data;
|
||||
pri_sch_mode->pri_id = pri_id;
|
||||
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
|
||||
if (ret) {
|
||||
dev_err(&hdev->pdev->dev,
|
||||
"failed to get priority sch mode, ret = %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
*mode = pri_sch_mode->sch_mode;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int hclge_tm_get_pri_weight(struct hclge_dev *hdev, u8 pri_id, u8 *weight)
|
||||
{
|
||||
struct hclge_priority_weight_cmd *priority_weight;
|
||||
struct hclge_desc desc;
|
||||
int ret;
|
||||
|
||||
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PRI_WEIGHT, true);
|
||||
priority_weight = (struct hclge_priority_weight_cmd *)desc.data;
|
||||
priority_weight->pri_id = pri_id;
|
||||
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
|
||||
if (ret) {
|
||||
dev_err(&hdev->pdev->dev,
|
||||
"failed to get priority weight, ret = %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
*weight = priority_weight->dwrr;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int hclge_tm_get_pri_shaper(struct hclge_dev *hdev, u8 pri_id,
|
||||
enum hclge_opcode_type cmd,
|
||||
struct hclge_pri_shaper_para *para)
|
||||
{
|
||||
struct hclge_pri_shapping_cmd *shap_cfg_cmd;
|
||||
struct hclge_desc desc;
|
||||
u32 shapping_para;
|
||||
int ret;
|
||||
|
||||
if (cmd != HCLGE_OPC_TM_PRI_C_SHAPPING &&
|
||||
cmd != HCLGE_OPC_TM_PRI_P_SHAPPING)
|
||||
return -EINVAL;
|
||||
|
||||
hclge_cmd_setup_basic_desc(&desc, cmd, true);
|
||||
shap_cfg_cmd = (struct hclge_pri_shapping_cmd *)desc.data;
|
||||
shap_cfg_cmd->pri_id = pri_id;
|
||||
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
|
||||
if (ret) {
|
||||
dev_err(&hdev->pdev->dev,
|
||||
"failed to get priority shaper(%#x), ret = %d\n",
|
||||
cmd, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
shapping_para = le32_to_cpu(shap_cfg_cmd->pri_shapping_para);
|
||||
para->ir_b = hclge_tm_get_field(shapping_para, IR_B);
|
||||
para->ir_u = hclge_tm_get_field(shapping_para, IR_U);
|
||||
para->ir_s = hclge_tm_get_field(shapping_para, IR_S);
|
||||
para->bs_b = hclge_tm_get_field(shapping_para, BS_B);
|
||||
para->bs_s = hclge_tm_get_field(shapping_para, BS_S);
|
||||
para->flag = shap_cfg_cmd->flag;
|
||||
para->rate = le32_to_cpu(shap_cfg_cmd->pri_rate);
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -21,6 +21,9 @@
|
|||
|
||||
#define HCLGE_ETHER_MAX_RATE 100000
|
||||
|
||||
#define HCLGE_TM_PF_MAX_PRI_NUM 8
|
||||
#define HCLGE_TM_PF_MAX_QSET_NUM 8
|
||||
|
||||
struct hclge_pg_to_pri_link_cmd {
|
||||
u8 pg_id;
|
||||
u8 rsvd1[3];
|
||||
|
|
@ -65,6 +68,18 @@ struct hclge_priority_weight_cmd {
|
|||
u8 dwrr;
|
||||
};
|
||||
|
||||
struct hclge_pri_sch_mode_cfg_cmd {
|
||||
u8 pri_id;
|
||||
u8 rsvd[3];
|
||||
u8 sch_mode;
|
||||
};
|
||||
|
||||
struct hclge_qs_sch_mode_cfg_cmd {
|
||||
__le16 qs_id;
|
||||
u8 rsvd[2];
|
||||
u8 sch_mode;
|
||||
};
|
||||
|
||||
struct hclge_qs_weight_cmd {
|
||||
__le16 qs_id;
|
||||
u8 dwrr;
|
||||
|
|
@ -173,6 +188,27 @@ struct hclge_shaper_ir_para {
|
|||
u8 ir_s; /* IR_S parameter of IR shaper */
|
||||
};
|
||||
|
||||
struct hclge_tm_nodes_cmd {
|
||||
u8 pg_base_id;
|
||||
u8 pri_base_id;
|
||||
__le16 qset_base_id;
|
||||
__le16 queue_base_id;
|
||||
u8 pg_num;
|
||||
u8 pri_num;
|
||||
__le16 qset_num;
|
||||
__le16 queue_num;
|
||||
};
|
||||
|
||||
struct hclge_pri_shaper_para {
|
||||
u8 ir_b;
|
||||
u8 ir_u;
|
||||
u8 ir_s;
|
||||
u8 bs_b;
|
||||
u8 bs_s;
|
||||
u8 flag;
|
||||
u32 rate;
|
||||
};
|
||||
|
||||
#define hclge_tm_set_field(dest, string, val) \
|
||||
hnae3_set_field((dest), \
|
||||
(HCLGE_TM_SHAP_##string##_MSK), \
|
||||
|
|
@ -195,5 +231,15 @@ int hclge_pause_addr_cfg(struct hclge_dev *hdev, const u8 *mac_addr);
|
|||
int hclge_pfc_rx_stats_get(struct hclge_dev *hdev, u64 *stats);
|
||||
int hclge_pfc_tx_stats_get(struct hclge_dev *hdev, u64 *stats);
|
||||
int hclge_tm_qs_shaper_cfg(struct hclge_vport *vport, int max_tx_rate);
|
||||
|
||||
int hclge_tm_get_qset_num(struct hclge_dev *hdev, u16 *qset_num);
|
||||
int hclge_tm_get_pri_num(struct hclge_dev *hdev, u8 *pri_num);
|
||||
int hclge_tm_get_qset_map_pri(struct hclge_dev *hdev, u16 qset_id, u8 *priority,
|
||||
u8 *link_vld);
|
||||
int hclge_tm_get_qset_sch_mode(struct hclge_dev *hdev, u16 qset_id, u8 *mode);
|
||||
int hclge_tm_get_qset_weight(struct hclge_dev *hdev, u16 qset_id, u8 *weight);
|
||||
int hclge_tm_get_pri_sch_mode(struct hclge_dev *hdev, u8 pri_id, u8 *mode);
|
||||
int hclge_tm_get_pri_weight(struct hclge_dev *hdev, u8 pri_id, u8 *weight);
|
||||
int hclge_tm_get_pri_shaper(struct hclge_dev *hdev, u8 pri_id,
|
||||
enum hclge_opcode_type cmd,
|
||||
struct hclge_pri_shaper_para *para);
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue