drm/amdgpu: expose vcn RB command
Signed-off-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -30,6 +30,13 @@
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#define AMDGPU_VCN_FIRMWARE_OFFSET 256
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#define AMDGPU_VCN_MAX_ENC_RINGS 3
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#define VCN_CMD_FENCE 0x00000000
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#define VCN_CMD_TRAP 0x00000001
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#define VCN_CMD_WRITE_REG 0x00000004
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#define VCN_CMD_REG_READ_COND_WAIT 0x00000006
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#define VCN_CMD_PACKET_START 0x0000000a
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#define VCN_CMD_PACKET_END 0x0000000b
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struct amdgpu_vcn {
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struct amdgpu_bo *vcpu_bo;
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void *cpu_addr;
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@ -512,7 +512,7 @@ static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64
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amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
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amdgpu_ring_write(ring,
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PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
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amdgpu_ring_write(ring, 0);
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amdgpu_ring_write(ring, VCN_CMD_FENCE << 1);
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amdgpu_ring_write(ring,
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PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
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@ -522,7 +522,7 @@ static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64
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amdgpu_ring_write(ring, 0);
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amdgpu_ring_write(ring,
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PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
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amdgpu_ring_write(ring, 2);
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amdgpu_ring_write(ring, VCN_CMD_TRAP << 1);
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}
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/**
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@ -576,7 +576,7 @@ static void vcn_v1_0_dec_vm_reg_write(struct amdgpu_ring *ring,
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amdgpu_ring_write(ring, data1);
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amdgpu_ring_write(ring,
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PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
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amdgpu_ring_write(ring, 8);
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amdgpu_ring_write(ring, VCN_CMD_WRITE_REG << 1);
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}
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static void vcn_v1_0_dec_vm_reg_wait(struct amdgpu_ring *ring,
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@ -593,7 +593,7 @@ static void vcn_v1_0_dec_vm_reg_wait(struct amdgpu_ring *ring,
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amdgpu_ring_write(ring, mask);
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amdgpu_ring_write(ring,
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PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
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amdgpu_ring_write(ring, 12);
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amdgpu_ring_write(ring, VCN_CMD_REG_READ_COND_WAIT << 1);
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}
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static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
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