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net: ipa: add more GSI register definitions 

Continue populating with GSI register definitions, adding remaining
registers whose offset depends on a channel ID.  Use gsi_reg() and
reg_n_offset() to determine offsets for those registers, and get rid
of the corresponding GSI_CH_C_*_OFFSET() macros.

Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Alex Elder 2023-02-10 13:36:51 -06:00 committed by David S. Miller
parent d2bb6e657f
commit 76924eb928
3 changed files with 62 additions and 38 deletions
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41
drivers/net/ipa/gsi.c
View File

@ -500,11 +500,14 @@ static void gsi_evt_ring_de_alloc_command(struct gsi *gsi, u32 evt_ring_id)
/* Fetch the current state of a channel from hardware */
static enum gsi_channel_state gsi_channel_state(struct gsi_channel *channel)
{
const struct reg *reg = gsi_reg(channel->gsi, CH_C_CNTXT_0);
u32 channel_id = gsi_channel_id(channel);
void __iomem *virt = channel->gsi->virt;
struct gsi *gsi = channel->gsi;
void __iomem *virt = gsi->virt;
u32 val;
val = ioread32(virt + GSI_CH_C_CNTXT_0_OFFSET(channel_id));
reg = gsi_reg(gsi, CH_C_CNTXT_0);
val = ioread32(virt + reg_n_offset(reg, channel_id));
return u32_get_bits(val, CHSTATE_FMASK);
}
@ -799,27 +802,34 @@ static void gsi_channel_program(struct gsi_channel *channel, bool doorbell)
struct gsi *gsi = channel->gsi;
const struct reg *reg;
u32 wrr_weight = 0;
u32 offset;
u32 val;
reg = gsi_reg(gsi, CH_C_CNTXT_0);
/* We program all channels as GPI type/protocol */
val = ch_c_cntxt_0_type_encode(gsi->version, GSI_CHANNEL_TYPE_GPI);
if (channel->toward_ipa)
val |= CHTYPE_DIR_FMASK;
val |= u32_encode_bits(channel->evt_ring_id, ERINDEX_FMASK);
val |= u32_encode_bits(GSI_RING_ELEMENT_SIZE, ELEMENT_SIZE_FMASK);
iowrite32(val, gsi->virt + GSI_CH_C_CNTXT_0_OFFSET(channel_id));
iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id));
reg = gsi_reg(gsi, CH_C_CNTXT_1);
val = ch_c_cntxt_1_length_encode(gsi->version, size);
iowrite32(val, gsi->virt + GSI_CH_C_CNTXT_1_OFFSET(channel_id));
iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id));
/* The context 2 and 3 registers store the low-order and
* high-order 32 bits of the address of the channel ring,
* respectively.
*/
reg = gsi_reg(gsi, CH_C_CNTXT_2);
val = lower_32_bits(channel->tre_ring.addr);
iowrite32(val, gsi->virt + GSI_CH_C_CNTXT_2_OFFSET(channel_id));
iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id));
reg = gsi_reg(gsi, CH_C_CNTXT_3);
val = upper_32_bits(channel->tre_ring.addr);
iowrite32(val, gsi->virt + GSI_CH_C_CNTXT_3_OFFSET(channel_id));
iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id));
reg = gsi_reg(gsi, CH_C_QOS);
@ -857,22 +867,27 @@ static void gsi_channel_program(struct gsi_channel *channel, bool doorbell)
GSI_RING_ELEMENT_SIZE;
gpi->outstanding_threshold = 2 * GSI_RING_ELEMENT_SIZE;
reg = gsi_reg(gsi, CH_C_SCRATCH_0);
val = scr.data.word1;
iowrite32(val, gsi->virt + GSI_CH_C_SCRATCH_0_OFFSET(channel_id));
iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id));
reg = gsi_reg(gsi, CH_C_SCRATCH_1);
val = scr.data.word2;
iowrite32(val, gsi->virt + GSI_CH_C_SCRATCH_1_OFFSET(channel_id));
iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id));
reg = gsi_reg(gsi, CH_C_SCRATCH_2);
val = scr.data.word3;
iowrite32(val, gsi->virt + GSI_CH_C_SCRATCH_2_OFFSET(channel_id));
iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id));
/* We must preserve the upper 16 bits of the last scratch register.
* The next sequence assumes those bits remain unchanged between the
* read and the write.
*/
val = ioread32(gsi->virt + GSI_CH_C_SCRATCH_3_OFFSET(channel_id));
reg = gsi_reg(gsi, CH_C_SCRATCH_3);
offset = reg_n_offset(reg, channel_id);
val = ioread32(gsi->virt + offset);
val = (scr.data.word4 & GENMASK(31, 16)) | (val & GENMASK(15, 0));
iowrite32(val, gsi->virt + GSI_CH_C_SCRATCH_3_OFFSET(channel_id));
iowrite32(val, gsi->virt + offset);
/* All done! */
}
@ -1506,11 +1521,13 @@ void gsi_channel_doorbell(struct gsi_channel *channel)
struct gsi_ring *tre_ring = &channel->tre_ring;
u32 channel_id = gsi_channel_id(channel);
struct gsi *gsi = channel->gsi;
const struct reg *reg;
u32 val;
reg = gsi_reg(gsi, CH_C_DOORBELL_0);
/* Note: index *must* be used modulo the ring count here */
val = gsi_ring_addr(tre_ring, tre_ring->index % tre_ring->count);
iowrite32(val, gsi->virt + GSI_CH_C_DOORBELL_0_OFFSET(channel_id));
iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id));
}
/* Consult hardware, move newly completed transactions to completed state */

27
drivers/net/ipa/gsi_reg.h
View File

@ -105,8 +105,7 @@ enum gsi_reg_id {
/* All other register offsets are relative to gsi->virt */
#define GSI_CH_C_CNTXT_0_OFFSET(ch) \
(0x0001c000 + 0x4000 * GSI_EE_AP + 0x80 * (ch))
/* CH_C_CNTXT_0 register */
#define CHTYPE_PROTOCOL_FMASK GENMASK(2, 0)
#define CHTYPE_DIR_FMASK GENMASK(3, 3)
#define EE_FMASK GENMASK(7, 4)
@ -131,15 +130,6 @@ enum gsi_channel_type {
GSI_CHANNEL_TYPE_11AD = 0x9,
};
#define GSI_CH_C_CNTXT_1_OFFSET(ch) \
(0x0001c004 + 0x4000 * GSI_EE_AP + 0x80 * (ch))
#define GSI_CH_C_CNTXT_2_OFFSET(ch) \
(0x0001c008 + 0x4000 * GSI_EE_AP + 0x80 * (ch))
#define GSI_CH_C_CNTXT_3_OFFSET(ch) \
(0x0001c00c + 0x4000 * GSI_EE_AP + 0x80 * (ch))
/* CH_C_QOS register */
#define WRR_WEIGHT_FMASK GENMASK(3, 0)
#define MAX_PREFETCH_FMASK GENMASK(8, 8)
@ -160,18 +150,6 @@ enum gsi_prefetch_mode {
GSI_FREE_PREFETCH = 0x3,
};
#define GSI_CH_C_SCRATCH_0_OFFSET(ch) \
(0x0001c060 + 0x4000 * GSI_EE_AP + 0x80 * (ch))
#define GSI_CH_C_SCRATCH_1_OFFSET(ch) \
(0x0001c064 + 0x4000 * GSI_EE_AP + 0x80 * (ch))
#define GSI_CH_C_SCRATCH_2_OFFSET(ch) \
(0x0001c068 + 0x4000 * GSI_EE_AP + 0x80 * (ch))
#define GSI_CH_C_SCRATCH_3_OFFSET(ch) \
(0x0001c06c + 0x4000 * GSI_EE_AP + 0x80 * (ch))
#define GSI_EV_CH_E_CNTXT_0_OFFSET(ev) \
(0x0001d000 + 0x4000 * GSI_EE_AP + 0x80 * (ev))
/* enum gsi_channel_type defines EV_CHTYPE field values in EV_CH_E_CNTXT_0 */
@ -221,9 +199,6 @@ enum gsi_prefetch_mode {
#define GSI_EV_CH_E_SCRATCH_1_OFFSET(ev) \
(0x0001d04c + 0x4000 * GSI_EE_AP + 0x80 * (ev))
#define GSI_CH_C_DOORBELL_0_OFFSET(ch) \
(0x0001e000 + 0x4000 * GSI_EE_AP + 0x08 * (ch))
#define GSI_EV_CH_E_DOORBELL_0_OFFSET(ev) \
(0x0001e100 + 0x4000 * GSI_EE_AP + 0x08 * (ev))

32
drivers/net/ipa/reg/gsi_reg-v3.1.c
View File

@ -8,10 +8,42 @@
#include "../reg.h"
#include "../gsi_reg.h"
REG_STRIDE(CH_C_CNTXT_0, ch_c_cntxt_0, 0x0001c000 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_CNTXT_1, ch_c_cntxt_1, 0x0001c004 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0001c008 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0001c00c + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_QOS, ch_c_qos, 0x0001c05c + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0,
0x0001c060 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1,
0x0001c064 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2,
0x0001c068 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3,
0x0001c06c + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0,
0x0001e000 + 0x4000 * GSI_EE_AP, 0x08);
static const struct reg *reg_array[] = {
[CH_C_CNTXT_0] = &reg_ch_c_cntxt_0,
[CH_C_CNTXT_1] = &reg_ch_c_cntxt_1,
[CH_C_CNTXT_2] = &reg_ch_c_cntxt_2,
[CH_C_CNTXT_3] = &reg_ch_c_cntxt_3,
[CH_C_QOS] = &reg_ch_c_qos,
[CH_C_SCRATCH_0] = &reg_ch_c_scratch_0,
[CH_C_SCRATCH_1] = &reg_ch_c_scratch_1,
[CH_C_SCRATCH_2] = &reg_ch_c_scratch_2,
[CH_C_SCRATCH_3] = &reg_ch_c_scratch_3,
[CH_C_DOORBELL_0] = &reg_ch_c_doorbell_0,
};
const struct regs gsi_regs_v3_1 = {