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drm/i915/xehpsdv: Define steering tables 

Define and initialize the MMIO ranges for which XeHP SDV requires MSLICE
and LNCF steering.

Bspec: 66534
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210729170008.2836648-3-matthew.d.roper@intel.com
This commit is contained in:
Matt Roper 2021-07-29 09:59:52 -07:00
parent 3ffe82d701
commit 768fe28dd3
2 changed files with 27 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
drivers/gpu/drm/i915/gt/intel_gt.c
View File

@ -89,6 +89,20 @@ static const struct intel_mmio_range icl_l3bank_steering_table[] = {
{}, {},
}; };
static const struct intel_mmio_range xehpsdv_mslice_steering_table[] = {
{ 0x004000, 0x004AFF },
{ 0x00C800, 0x00CFFF },
{ 0x00DD00, 0x00DDFF },
{ 0x00E900, 0x00FFFF }, /* 0xEA00 - OxEFFF is unused */
{},
};
static const struct intel_mmio_range xehpsdv_lncf_steering_table[] = {
{ 0x00B000, 0x00B0FF },
{ 0x00D800, 0x00D8FF },
{},
};
static u16 slicemask(struct intel_gt *gt, int count) static u16 slicemask(struct intel_gt *gt, int count)
{ {
u64 dss_mask = intel_sseu_get_subslices(&gt->info.sseu, 0); u64 dss_mask = intel_sseu_get_subslices(&gt->info.sseu, 0);
@ -115,7 +129,10 @@ int intel_gt_init_mmio(struct intel_gt *gt)
(intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) & (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
GEN12_MEML3_EN_MASK); GEN12_MEML3_EN_MASK);
if (GRAPHICS_VER(i915) >= 11 && if (IS_XEHPSDV(i915)) {
gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
gt->steering_table[LNCF] = xehpsdv_lncf_steering_table;
} else if (GRAPHICS_VER(i915) >= 11 &&
GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) { GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) {
gt->steering_table[L3BANK] = icl_l3bank_steering_table; gt->steering_table[L3BANK] = icl_l3bank_steering_table;
gt->info.l3bank_mask = gt->info.l3bank_mask =

11
drivers/gpu/drm/i915/gt/intel_workarounds.c
View File

@ -934,7 +934,6 @@ icl_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
__add_mcr_wa(i915, wal, slice, subslice); __add_mcr_wa(i915, wal, slice, subslice);
} }
__maybe_unused
static void static void
xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
{ {
@ -1136,10 +1135,18 @@ dg1_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
VSUNIT_CLKGATE_DIS_TGL); VSUNIT_CLKGATE_DIS_TGL);
} }
static void
xehpsdv_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
xehp_init_mcr(&i915->gt, wal);
}
static void static void
gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
{ {
if (IS_DG1(i915)) if (IS_XEHPSDV(i915))
xehpsdv_gt_workarounds_init(i915, wal);
else if (IS_DG1(i915))
dg1_gt_workarounds_init(i915, wal); dg1_gt_workarounds_init(i915, wal);
else if (IS_TIGERLAKE(i915)) else if (IS_TIGERLAKE(i915))
tgl_gt_workarounds_init(i915, wal); tgl_gt_workarounds_init(i915, wal);