drm/amd/display: Update bouding box values for DCN32
All clock values came from firmware, but bounding box values can be helpful in some debug situations. This commit updates some of the values associated with clock speed and memory channels. Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -109,7 +109,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc = {
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{
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.state = 0,
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.dcfclk_mhz = 1564.0,
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.fabricclk_mhz = 400.0,
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.fabricclk_mhz = 2500.0,
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.dispclk_mhz = 2150.0,
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.dppclk_mhz = 2150.0,
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.phyclk_mhz = 810.0,
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@ -117,7 +117,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc = {
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.phyclk_d32_mhz = 625.0,
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.socclk_mhz = 1200.0,
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.dscclk_mhz = 716.667,
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.dram_speed_mts = 16000.0,
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.dram_speed_mts = 18000.0,
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.dtbclk_mhz = 1564.0,
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},
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},
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@ -148,7 +148,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc = {
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.max_avg_fabric_bw_use_normal_percent = 60.0,
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.max_avg_dram_bw_use_normal_strobe_percent = 50.0,
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.max_avg_dram_bw_use_normal_percent = 15.0,
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.num_chans = 8,
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.num_chans = 24,
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.dram_channel_width_bytes = 2,
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.fabric_datapath_to_dcn_data_return_bytes = 64,
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.return_bus_width_bytes = 64,
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