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drm/i915: Implement UHBR bandwidth check 

According to spec, we should check if output_bpp * pixel_rate is less
than DDI clock * 72, if UHBR is used.

v2: - s/pipe_config/crtc_state/ (Jani Nikula)
    - Merged previous patch into that one, to remove empty function(Jani Nikula)

v3: - Make that constraint check to be DSC-related only
    - Limit this to only DISPLAY_VER <= 13

v4: - Move constraint check to the top(Vinod Govindapillai)

HSDES: 1406899791
BSPEC: 49259

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230324135125.6720-1-stanislav.lisovskiy@intel.com
This commit is contained in:
Stanislav Lisovskiy 2023-03-24 15:51:25 +02:00
parent aaee4bbe8a
commit 764b1c8df4
1 changed files with 29 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

33
drivers/gpu/drm/i915/display/intel_dp_mst.c
View File

@ -45,6 +45,27 @@
#include "intel_hotplug.h"
#include "skl_scaler.h"
static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp,
const struct drm_display_mode *adjusted_mode,
struct intel_crtc_state *crtc_state,
bool dsc)
{
if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) <= 13 && dsc) {
int output_bpp = bpp;
/* DisplayPort 2 128b/132b, bits per lane is always 32 */
int symbol_clock = crtc_state->port_clock / 32;
if (output_bpp * adjusted_mode->crtc_clock >=
symbol_clock * 72) {
drm_dbg_kms(&i915->drm, "UHBR check failed(required bw %d available %d)\n",
output_bpp * adjusted_mode->crtc_clock, symbol_clock * 72);
return -EINVAL;
}
}
return 0;
}
static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
int max_bpp,
@ -81,12 +102,16 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
}
for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) {
drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp);
ret = intel_dp_mst_check_constraints(i915, bpp, adjusted_mode, crtc_state, dsc);
if (ret)
continue;
crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock,
dsc ? bpp << 4 : bpp,
dsc);
drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp);
slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
connector->port,
crtc_state->pbn);
@ -104,8 +129,8 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
}
}
/* Despite slots are non-zero, we still failed the atomic check */
if (ret && slots >= 0)
/* We failed to find a proper bpp/timeslots, return error */
if (ret)
slots = ret;
if (slots < 0) {