gru: send cross partition interrupts using the gru
GRU Message queue instructions are used to deliver messages to other SSIs within the numalink domain. In most cases, a single GRU mesq instruction will deliver both the message AND an interrupt to notify the other SSI that a messsage is present. In some cases, however, the interrupt must be sent explicitly. To improve resilency, the GRU driver should send these explicit interrupts using the GRU to write the remote chipset register. Current code sends the interrupt using a cpu instruction to write the chipset register. Signed-off-by: Jack Steiner <steiner@sgi.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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@ -367,6 +367,18 @@ static inline void gru_vload_phys(void *cb, unsigned long gpa,
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(unsigned long)tri0, CB_IMA(hints)));
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}
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static inline void gru_vstore_phys(void *cb, unsigned long gpa,
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unsigned int tri0, int iaa, unsigned long hints)
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{
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struct gru_instruction *ins = (struct gru_instruction *)cb;
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ins->baddr0 = (long)gpa | ((unsigned long)iaa << 62);
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ins->nelem = 1;
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ins->op1_stride = 1;
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gru_start_instruction(ins, __opdword(OP_VSTORE, 0, XTYPE_DW, iaa, 0,
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(unsigned long)tri0, CB_IMA(hints)));
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}
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static inline void gru_vload(void *cb, unsigned long mem_addr,
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unsigned int tri0, unsigned char xtype, unsigned long nelem,
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unsigned long stride, unsigned long hints)
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@ -31,6 +31,7 @@
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#include <linux/interrupt.h>
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#include <linux/uaccess.h>
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#include <linux/delay.h>
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#include <asm/io_apic.h>
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#include "gru.h"
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#include "grulib.h"
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#include "grutables.h"
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@ -566,7 +567,7 @@ int gru_create_message_queue(struct gru_message_queue_desc *mqd,
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mqd->mq = mq;
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mqd->mq_gpa = uv_gpa(mq);
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mqd->qlines = qlines;
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mqd->interrupt_pnode = UV_NASID_TO_PNODE(nasid);
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mqd->interrupt_pnode = nasid >> 1;
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mqd->interrupt_vector = vector;
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mqd->interrupt_apicid = apicid;
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return 0;
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@ -702,18 +703,6 @@ cberr:
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return MQE_UNEXPECTED_CB_ERR;
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}
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/*
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* Send a cross-partition interrupt to the SSI that contains the target
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* message queue. Normally, the interrupt is automatically delivered by hardware
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* but some error conditions require explicit delivery.
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*/
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static void send_message_queue_interrupt(struct gru_message_queue_desc *mqd)
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{
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if (mqd->interrupt_vector)
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uv_hub_send_ipi(mqd->interrupt_pnode, mqd->interrupt_apicid,
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mqd->interrupt_vector);
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}
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/*
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* Handle a PUT failure. Note: if message was a 2-line message, one of the
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* lines might have successfully have been written. Before sending the
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@ -723,7 +712,8 @@ static void send_message_queue_interrupt(struct gru_message_queue_desc *mqd)
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static int send_message_put_nacked(void *cb, struct gru_message_queue_desc *mqd,
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void *mesg, int lines)
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{
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unsigned long m;
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unsigned long m, *val = mesg, gpa, save;
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int ret;
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m = mqd->mq_gpa + (gru_get_amo_value_head(cb) << 6);
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if (lines == 2) {
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@ -734,7 +724,26 @@ static int send_message_put_nacked(void *cb, struct gru_message_queue_desc *mqd,
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gru_vstore(cb, m, gru_get_tri(mesg), XTYPE_CL, lines, 1, IMA);
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if (gru_wait(cb) != CBS_IDLE)
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return MQE_UNEXPECTED_CB_ERR;
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send_message_queue_interrupt(mqd);
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if (!mqd->interrupt_vector)
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return MQE_OK;
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/*
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* Send a cross-partition interrupt to the SSI that contains the target
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* message queue. Normally, the interrupt is automatically delivered by
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* hardware but some error conditions require explicit delivery.
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* Use the GRU to deliver the interrupt. Otherwise partition failures
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* could cause unrecovered errors.
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*/
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gpa = uv_global_gru_mmr_address(mqd->interrupt_pnode, UVH_IPI_INT);
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save = *val;
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*val = uv_hub_ipi_value(mqd->interrupt_apicid, mqd->interrupt_vector,
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dest_Fixed);
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gru_vstore_phys(cb, gpa, gru_get_tri(mesg), IAA_REGISTER, IMA);
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ret = gru_wait(cb);
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*val = save;
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if (ret != CBS_IDLE)
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return MQE_UNEXPECTED_CB_ERR;
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return MQE_OK;
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}
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